soc/intel/cnl: replace the remains of HeciEnabled by device state in dt

The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.

Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.

Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.

Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/hatch/variants/ambassador/overridetree.cb

@@ -1,7 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
-
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
 
@@ -370,6 +367,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/genesis/overridetree.cb

@@ -1,7 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
-
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
 
@@ -370,6 +367,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/prodrive/hermes/devicetree.cb

@@ -24,9 +24,7 @@ chip soc/intel/cannonlake
 		device pci 14.2 on  end # RAM controller
 		device pci 14.5 off end # SDCard
 
-		device pci 16.0 on      # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
-			register "HeciEnabled" = "1"
-		end
 		device pci 16.1 on  end # Management Engine Interface 2
 		device pci 16.4 off end # Management Engine Interface 3
 		device pci 17.0 on  end # SATA

src/mainboard/siemens/chili/variants/base/devicetree.cb

@@ -48,9 +48,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 off	end	# I2C #1
 		device pci 15.2 off	end	# I2C #2
 		device pci 15.3 off	end	# I2C #3
-		device pci 16.0 on		# Management Engine Interface 1
+		device pci 16.0 on	end	# Management Engine Interface 1
-			register "HeciEnabled" = "1"
-		end
 		device pci 16.1 off	end	# Management Engine Interface 2
 		device pci 16.2 off	end	# Management Engine IDE-R
 		device pci 16.3 off	end	# Management Engine KT Redirection

src/mainboard/siemens/chili/variants/chili/devicetree.cb

@@ -100,9 +100,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 off	end	# I2C #1
 		device pci 15.2 off	end	# I2C #2
 		device pci 15.3 off	end	# I2C #3
-		device pci 16.0 on		# Management Engine Interface 1
+		device pci 16.0 on	end	# Management Engine Interface 1
-			register "HeciEnabled" = "1"
-		end
 		device pci 16.1 off	end	# Management Engine Interface 2
 		device pci 16.2 off	end	# Management Engine IDE-R
 		device pci 16.3 off	end	# Management Engine KT Redirection

src/soc/intel/cannonlake/chip.h

@@ -253,9 +253,6 @@ struct soc_intel_cannonlake_config {
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */
 	struct vr_config domain_vr_config[NUM_VR_DOMAINS];
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
 
 	/* Enables support for Teton Glacier hybrid storage device */
 	uint8_t TetonGlacierMode;

src/soc/intel/cannonlake/smihandler.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <device/pci_def.h>
+#include <device/device.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
 #include <soc/soc_chip.h>
@@ -17,11 +17,11 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_cannonlake_config *config;
+	if (!CONFIG(HECI_DISABLE_USING_SMM))
+		return;
 
-	config = config_of_soc();
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
-
+	if (!is_dev_enabled(dev))
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
 		heci_disable();
 }