{drivers,mainboard}: Move FSP logo support to fsp1_1

Support to display a logo using FSP 1.1 currently resides in facebook fbg1701
mainboard.

The related support is moved to drivers/intel/fsp1_1 and used by the
Facebook fbg1701 mainboard. The storage for the uncompressed logo
is changed. We don't use .bss any longer as the logo doesn't need to be
available at runtime.

BUG=N/A
TEST=booting Facebook fbg1701

Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

src/drivers/intel/fsp1_1/Kconfig

@@ -91,4 +91,16 @@ config SKIP_FSP_CAR
 	help
 	  Selected by platforms that implement their own CAR setup.
 
+config FSP1_1_DISPLAY_LOGO
+	bool "Enable logo"
+	default n
+	help
+	  Uses the FSP to display the boot logo. This method supports a
+	  BMP file only. The uncompressed size can be up to 1 MB.
+
+config FSP1_1_LOGO_FILE_NAME
+	string "Logo file"
+	depends on FSP1_1_DISPLAY_LOGO
+	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp"
+
 endif #PLATFORM_USES_FSP1_1

src/drivers/intel/fsp1_1/Makefile.inc

@@ -32,6 +32,7 @@ ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
 ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
+ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
 ramstage-$(CONFIG_MMA) += mma_core.c
@@ -53,4 +54,10 @@ fsp.bin-options := --xip $(TXTIBB)
 fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC)
 endif
 
+# Add logo to the cbfs image
+cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp
+logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
+logo.bmp-type := raw
+logo.bmp-compression := LZMA
+
 endif

src/drivers/intel/fsp1_1/include/fsp/ramstage.h

@@ -33,6 +33,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params);
 void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	SILICON_INIT_UPD *new);
+void load_logo(SILICON_INIT_UPD *params);
 void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
 
 #endif /* _INTEL_COMMON_RAMSTAGE_H_ */

src/drivers/intel/fsp1_1/logo.c

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include <console/console.h>
+#include <fsp/ramstage.h>
+#include <include/cbfs.h>
+
+void load_logo(SILICON_INIT_UPD *params)
+{
+	params->PcdLogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->PcdLogoPtr,
+						  params->PcdLogoSize, CBFS_TYPE_RAW);
+	if (!params->PcdLogoSize)
+		params->PcdLogoPtr = 0;
+}

src/drivers/intel/fsp1_1/ramstage.c

@@ -21,6 +21,7 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
+#include <cbmem.h>
 
 /* SOC initialization after FSP silicon init */
 __weak void soc_after_silicon_init(void)
@@ -68,6 +69,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	EFI_STATUS status;
 	UPD_DATA_REGION *upd_ptr;
 	VPD_DATA_REGION *vpd_ptr;
+	const struct cbmem_entry *logo_entry;
 
 	/* Display the FSP header */
 	if (fsp_info_header == NULL) {
@@ -94,6 +96,14 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 		load_vbt(is_s3_wakeup, &silicon_init_params);
 	mainboard_silicon_init_params(&silicon_init_params);
 
+	if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) {
+		silicon_init_params.PcdLogoSize = 1 * MiB;
+		logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO,
+					     silicon_init_params.PcdLogoSize);
+		silicon_init_params.PcdLogoPtr = (UINT32)cbmem_entry_start(logo_entry);
+		load_logo(&silicon_init_params);
+	}
+
 	/* Display the UPD data */
 	if (CONFIG(DISPLAY_UPD_DATA))
 		soc_display_silicon_init_params(original_params,
@@ -111,6 +121,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
 	printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
 
+	/* The logo_entry can be freed up now as it is not required any longer */
+	if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup)
+		cbmem_entry_remove(logo_entry);
+
 	/* Mark graphics init done after SiliconInit if VBT was provided */
 #if CONFIG(RUN_FSP_GOP)
 	/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs