soc/intel/skylake: Set PsysPl3 and Pl4

If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.

BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
     expected.  Test on Fizz, which will set these values in
     mainboard.

Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>

src/soc/intel/skylake/chip.h

@@ -100,6 +100,16 @@ struct soc_intel_skylake_config {
 	/* SysPL2 Value in Watts */
 	u32 tdp_psyspl2;
 
+	/* SysPL3 Value in Watts */
+	u32 tdp_psyspl3;
+	/* SysPL3 window size */
+	u32 tdp_psyspl3_time;
+	/* SysPL3 duty cycle */
+	u32 tdp_psyspl3_dutycycle;
+
+	/* PL4 Value in Watts */
+	u32 tdp_pl4;
+
 	/*
 	 * The following fields come from FspUpdVpd.h.
 	 * These are configuration values that are passed to FSP during