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soc/intel/skylake: Set PsysPl3 and Pl4

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If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.

BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
     expected.  Test on Fizz, which will set these values in
     mainboard.

Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
This commit is contained in:
Shelley Chen
2018-01-31 15:55:50 -08:00
committed by Shelley Chen
parent 1177bf5165
commit 50db9a208e
4 changed files with 45 additions and 0 deletions
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32
src/soc/intel/skylake/cpu.c
View File

@@ -191,6 +191,38 @@ void set_power_limits(u8 power_limit_1_time)
wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
}
/* Set PsysPl3 */
if (conf->tdp_psyspl3) {
limit = rdmsr(MSR_PL3_CONTROL);
limit.lo = 0;
printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
conf->tdp_psyspl3);
limit.lo |= (conf->tdp_psyspl3 * power_unit) &
PKG_POWER_LIMIT_MASK;
/* Enable PsysPl3 */
limit.lo |= PKG_POWER_LIMIT_EN;
/* set PsysPl3 time window */
limit.lo |= (conf->tdp_psyspl3_time &
PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT;
/* set PsysPl3 duty cycle */
limit.lo |= (conf->tdp_psyspl3_dutycycle &
PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
wrmsr(MSR_PL3_CONTROL, limit);
}
/* Set Pl4 */
if (conf->tdp_pl4) {
limit = rdmsr(MSR_VR_CURRENT_CONFIG);
limit.lo = 0;
printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
conf->tdp_pl4);
limit.lo |= (conf->tdp_pl4 * power_unit) &
PKG_POWER_LIMIT_MASK;
wrmsr(MSR_VR_CURRENT_CONFIG, limit);
}
/* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);