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I just went on a bugfix frenzy and fixed all printk format warnings

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triggered by the AMD 690/SB600 targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Carl-Daniel Hailfinger
2009-03-04 01:06:41 +00:00
parent 4b95ced365
commit 51001fbd81
18 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/rs690/rs690.c
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@@ -129,7 +129,7 @@ void rs690_enable(device_t dev)
device_t nb_dev = 0, sb_dev = 0;
int dev_ind;
printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev));
printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!nb_dev) {

4
src/southbridge/amd/rs690/rs690_gfx.c
View File

@@ -121,7 +121,7 @@ static void rs690_internal_gfx_enable(device_t dev)
device_t k8_f0 = 0, k8_f2 = 0;
device_t nb_dev = dev_find_slot(0, 0);
printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev,
printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
nb_dev);
/* set APERTURE_SIZE, 128M. */
@@ -417,7 +417,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
struct southbridge_amd_rs690_config *cfg =
(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n",
printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
nb_dev, dev, port);
/* step 0, REFCLK_SEL, skip A11 revision */

2
src/southbridge/amd/rs690/rs690_pcie.c
View File

@@ -203,7 +203,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
device_t sb_dev;
struct southbridge_amd_rs690_config *cfg =
(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port);
printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
/* init GPP core */
set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,

2
src/southbridge/amd/sb600/sb600_hda.c
View File

@@ -302,7 +302,7 @@ static void hda_init(struct device *dev)
return;
base = (u8 *) ((u32)res->base);
printk_debug("base = %08x\n", base);
printk_debug("base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {

2
src/southbridge/amd/sb600/sb600_sata.c
View File

@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */
printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */
printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */
printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */
printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* Program the 2C to 0x43801002 */
dword = 0x43801002;

2
src/southbridge/amd/sb600/sb600_usb.c
View File

@@ -94,7 +94,7 @@ static void usb_init2(struct device *dev)
/* pci_write_config32(dev, 0xf8, dword); */
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
printk_info("usb2_bar0=%x\n", usb2_bar0);
printk_info("usb2_bar0=%p\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;