This is so that people can see it. This is the sb600 for v3. It almost
certainly won't build -- that comes later. I am hoping to get some eyeballs on it for simple errors. rs690 is next. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
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src/southbridge/amd/sb600/sata.c
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200
src/southbridge/amd/sb600/sata.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "sb600.h"
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static void sata_init(struct device *dev)
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{
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u8 byte;
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u16 word;
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u32 dword;
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u8 *sata_bar5;
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u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
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struct southbridge_ati_sb600_sata_dts_config *conf;
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conf = dev->device_configuration;
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struct device * sm_dev;
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/* SATA SMBus Disable */
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/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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/* Disable SATA SMBUS */
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 1);
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/* Enable SATA and power saving */
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= (1 << 0);
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byte |= (1 << 5);
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pci_write_config8(sm_dev, 0xad, byte);
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/* Set the interrupt Mapping to INTG# */
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byte = pci_read_config8(sm_dev, 0xaf);
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byte = 0x6 << 2;
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pci_write_config8(sm_dev, 0xaf, byte);
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/* get base addresss */
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sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF);
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sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
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sata_bar1 = pci_read_config16(dev, 0x14) & ~0x7;
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sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
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sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
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sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;
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printk(BIOS_DEBUG, "sata_bar0=%x\n", sata_bar0); /* 3030 */
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printk(BIOS_DEBUG, "sata_bar1=%x\n", sata_bar1); /* 3070 */
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printk(BIOS_DEBUG, "sata_bar2=%x\n", sata_bar2); /* 3040 */
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printk(BIOS_DEBUG, "sata_bar3=%x\n", sata_bar3); /* 3080 */
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printk(BIOS_DEBUG, "sata_bar4=%x\n", sata_bar4); /* 3000 */
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printk(BIOS_DEBUG, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
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/* Program the 2C to 0x43801002 */
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dword = 0x43801002;
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pci_write_config32(dev, 0x2c, dword);
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/* SERR-Enable */
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word = pci_read_config16(dev, 0x04);
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word |= (1 << 8);
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pci_write_config16(dev, 0x04, word);
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/* Dynamic power saving */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Set SATA Operation Mode, Set to IDE mode */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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byte |= (1 << 4);
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pci_write_config8(dev, 0x40, byte);
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dword = 0x01018f00;
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pci_write_config32(dev, 0x8, dword);
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byte = pci_read_config8(dev, 0x40);
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byte &= ~(1 << 0);
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pci_write_config8(dev, 0x40, byte);
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/* Enable the SATA watchdog counter */
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byte = pci_read_config8(dev, 0x44);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x44, byte);
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/* Program the watchdog counter to 0x10 */
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byte = 0x10;
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pci_write_config8(dev, 0x46, byte);
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/* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
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word = 0x2c00;
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pci_write_config16(dev, 0x86, word);
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/* RPR6.5 Program the Phy Tuning4Ports */
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dword = 0x00B401D6;
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pci_write_config32(dev, 0x88, dword);
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pci_write_config32(dev, 0x8c, dword);
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pci_write_config32(dev, 0x90, dword);
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pci_write_config32(dev, 0x94, dword);
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byte = 0xB8;
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pci_write_config8(dev, 0xA5, byte);
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pci_write_config8(dev, 0xAD, byte);
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pci_write_config8(dev, 0xB5, byte);
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pci_write_config8(dev, 0xBD, byte);
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/* RPR 6.8 */
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word = pci_read_config16(dev, 0x42);
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word |= 1 << 7;
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pci_write_config16(dev, 0x42, word);
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/* RPR 6.9 */
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dword = pci_read_config32(dev, 0x40);
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dword |= 1 << 25;
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pci_write_config32(dev, 0x40, dword);
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/* Enable the I/O ,MM ,BusMaster access for SATA */
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byte = pci_read_config8(dev, 0x4);
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byte |= 7 << 0;
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pci_write_config8(dev, 0x4, byte);
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/* RPR6.6 SATA drive detection. Currently we detect Primary Master Device only */
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/* Use BAR5+0x1A8,BAR0+0x6 for Primary Slave */
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/* Use BAR5+0x228,BAR0+0x6 for Secondary Master */
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/* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
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byte = readb(sata_bar5 + 0x128);
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printk(BIOS_DEBUG, "byte=%x\n", byte);
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byte &= 0xF;
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if (byte == 0x3) {
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outb(0xA0, sata_bar0 + 0x6);
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while ((inb(sata_bar0 + 0x6) != 0xA0)
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|| ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
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mdelay(10);
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printk(BIOS_DEBUG, "0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
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inb(sata_bar0 + 0x7));
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printk(BIOS_DEBUG, "drive detection fail,trying...\n");
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}
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printk(BIOS_DEBUG, "Primary master device is ready\n");
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} else {
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printk(BIOS_DEBUG, "No Primary master SATA drive on Slot0\n");
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}
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/* Below is CIM InitSataLateFar */
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/* Enable interrupts from the HBA */
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byte = readb(sata_bar5 + 0x4);
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byte |= 1 << 1;
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writeb(byte, (sata_bar5 + 0x4));
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/* Clear error status */
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writel(0xFFFFFFFF, (sata_bar5 + 0x130));
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writel(0xFFFFFFFF, (sata_bar5 + 0x1b0));
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writel(0xFFFFFFFF, (sata_bar5 + 0x230));
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writel(0xFFFFFFFF, (sata_bar5 + 0x2b0));
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/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
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/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
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/* word = 0x0000; */
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/* word = pm_ioread(0x28); */
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/* byte = pm_ioread(0x29); */
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/* word |= byte<<8; */
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/* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
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/* writel(0x80000000 , word); */
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}
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static struct pci_operations lops_pci = {
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/* .set_subsystem = pci_dev_set_subsystem, */
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};
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struct device_operations amd8111_ide = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB600_SATA}}},
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.constructor = default_device_constructor,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = sata_init,
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.ops_pci = &lops_pci
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};
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