soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
2020-03-25 13:20:34 +05:30
committed by Subrata Banik
parent dd7acaad27
commit 512b77abb5
66 changed files with 939 additions and 3250 deletions

View File

@@ -176,8 +176,8 @@ static void soc_enable(struct device *dev)
dev->ops = &cpu_bus_ops;
}
struct chip_operations soc_intel_tigerlake_ops = {
CHIP_NAME("Intel Tigerlake")
struct chip_operations soc_intel_jasperlake_ops = {
CHIP_NAME("Intel Jasperlake")
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
};