soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
committed by
Subrata Banik
Subrata Banik
parent
dd7acaad27
commit
512b77abb5
191
src/soc/intel/jasperlake/fsp_params.c
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191
src/soc/intel/jasperlake/fsp_params.c
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/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <fsp/ppi/mp_service_ppi.h>
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#include <fsp/util.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/xdci.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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const struct soc_intel_jasperlake_config *config = config_of_soc();
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/* LPSS controllers configuration */
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/* I2C */
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_Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >=
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ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
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memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode,
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sizeof(config->SerialIoI2cMode));
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/* GSPI */
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >=
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ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!");
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memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode,
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sizeof(config->SerialIoGSpiMode));
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >=
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ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!");
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memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode,
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sizeof(config->SerialIoGSpiCsMode));
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_Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >=
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ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!");
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memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState,
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sizeof(config->SerialIoGSpiCsState));
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/* UART */
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_Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >=
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ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!");
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memcpy(params->SerialIoUartMode, config->SerialIoUartMode,
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sizeof(config->SerialIoUartMode));
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}
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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unsigned int i;
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struct device *dev;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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struct soc_intel_jasperlake_config *config = config_of_soc();
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/* Parse device tree and fill in FSP UPDs */
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parse_devicetree(params);
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/* Load VBT before devicetree-specific config. */
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params->GraphicsConfigPtr = (uintptr_t)vbt_get();
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/* Check if IGD is present and fill Graphics init param accordingly */
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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/* Use coreboot MP PPI services if Kconfig is enabled */
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if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
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params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
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params->SkipMpInit = 0;
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} else {
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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}
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/* Unlock upper 8 bytes of RTC RAM */
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params->RtcMemoryLock = 0;
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
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params->Enable8254ClockGatingOnS3 = 1;
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* USB configuration */
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
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params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
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params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
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params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
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params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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/* SDCard related configuration */
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dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
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if (!dev)
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params->ScsSdCardEnabled = 0;
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else
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params->ScsSdCardEnabled = dev->enabled;
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params->Device4Enable = config->Device4Enable;
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/* eMMC configuration */
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dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
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if (!dev) {
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params->ScsEmmcEnabled = 0;
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} else {
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params->ScsEmmcEnabled = dev->enabled;
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params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
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}
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
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if (dev) {
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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} else {
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params->XdciEnable = 0;
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}
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/* Provide correct UART number for FSP debug logs */
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params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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/* Override/Fill FSP Silicon Param for mainboard */
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mainboard_silicon_init_params(params);
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Return list of SOC LPSS controllers */
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const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
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{
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*size = ARRAY_SIZE(serial_io_dev);
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return serial_io_dev;
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}
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