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soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

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This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
2020-03-25 13:20:34 +05:30
committed by Subrata Banik
parent dd7acaad27
commit 512b77abb5
66 changed files with 939 additions and 3250 deletions
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6
src/soc/intel/jasperlake/pmc.c
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@ -12,12 +12,6 @@
* GNU General Public License for more details.
*/
/*
* This file is created based on Intel Tiger Lake Processor PCH Datasheet
* Document number: 575857
* Chapter number: 4
*/
#include <bootstate.h>
#include <console/console.h>
#include <device/mmio.h>