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arch/x86 cbmem: Drop tests for LATE_CBMEM_INIT

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Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.

This also removes all references to LATE_CBMEM_INIT
in comments.

Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2018-06-03 12:29:50 +03:00
committed by Patrick Georgi
parent 8616442150
commit 513a1a81f7
15 changed files with 28 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/car.ld
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@@ -43,7 +43,7 @@
* in size. Therefore place them at the beginning .car.data section
* so that multiple stages (romstage and verstage) have a consistent
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : CONFIG_PRERAM_CBMEM_CONSOLE_SIZE))
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
. = ALIGN(32);
/* Page directory pointer table resides here. There are 4 8-byte entries

44
src/arch/x86/cbmem.c
View File

@@ -15,55 +15,23 @@
#include <cbmem.h>
#include <arch/acpi.h>
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
void __weak backup_top_of_low_cacheable(uintptr_t ramtop)
{
/* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
*/
}
uintptr_t __weak restore_top_of_low_cacheable(void)
{
return 0;
}
#endif /* LATE_CBMEM_INIT */
#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
static void *cbmem_top_backup;
void set_late_cbmem_top(uintptr_t ramtop)
{
backup_top_of_low_cacheable(ramtop);
if (ENV_RAMSTAGE)
cbmem_top_backup = (void *)ramtop;
}
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
uintptr_t __weak restore_cbmem_top(void)
{
if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE)
if (!acpi_is_wakeup_s3())
return 0;
return restore_top_of_low_cacheable();
}
void *cbmem_top(void)
{
uintptr_t top_backup;
static void *cbmem_top_backup;
void *top_backup;
if (ENV_RAMSTAGE && cbmem_top_backup != NULL)
return cbmem_top_backup;
top_backup = restore_cbmem_top();
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
top_backup = (void *)restore_top_of_low_cacheable();
if (ENV_RAMSTAGE)
cbmem_top_backup = (void *)top_backup;
cbmem_top_backup = top_backup;
return (void *)top_backup;
return top_backup;
}
#endif /* CBMEM_TOP_BACKUP */

5
src/arch/x86/include/arch/cpu.h
View File

@@ -270,11 +270,6 @@ struct postcar_frame {
*/
int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
/*
* Initialize postcar_frame object with a fixed stacktop in low memory.
*/
void postcar_frame_init_lowmem(struct postcar_frame *pcf);
/*
* Add variable MTRR covering the provided range with MTRR type.
*/

10
src/arch/x86/postcar_loader.c
View File

@@ -60,16 +60,6 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
return 0;
}
/*
* For use with LATE_CBMEM_INIT boards only, with a fixed stacktop in
* low memory.
*/
void postcar_frame_init_lowmem(struct postcar_frame *pcf)
{
postcar_frame_prepare(pcf);
pcf->stack = CONFIG_RAMTOP;
}
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{