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mb/google/brox: Fix GPIO assignments in gpio.h

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Assigning the macros in gpio.h to the correct GPIOs.  Also, fixing GPE
configurations so that they are mapped to the proper wake sources
(GPP_B, D, E groups).

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Shelley Chen 2023-11-07 14:22:30 -08:00
parent 653f349f2f
commit 513d54708d
2 changed files with 8 additions and 8 deletions
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6
src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
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@ -1,9 +1,9 @@
chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"
register "pmc_gpe0_dw2" = "GPP_F"
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"

10
src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
View File

@ -8,13 +8,13 @@
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
#define GPE_EC_WAKE GPE0_DW2_17
/* EC wake is EC_PCH_INT which is routed to GPP_D1 pin */
#define GPE_EC_WAKE GPE0_DW1_01
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E15
#define GPIO_PCH_WP GPP_E8
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F9
#define GPIO_SLP_S0_GATE GPP_D17
/* GPIO IRQ for tight timestamps / wake support */
#define EC_SYNC_IRQ GPP_F17_IRQ
#define EC_SYNC_IRQ GPP_D1_IRQ
#endif /* __BASEBOARD_GPIO_H__ */