diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index c40b31ed5a..fb0f9d26af 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -117,6 +117,23 @@ Device (PEG0)
 	Name (_ADR, 0x00060000)
 }
 
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+Device (PEG1)
+{
+	Name (_ADR, 0x00010000)
+}
+
+Device (PEG2)
+{
+	Name (_ADR, 0x00010001)
+}
+
+Device (PEG3)
+{
+	Name (_ADR, 0x00010002)
+}
+#endif
+
 Device (RP01)
 {
 	Name (_ADR, 0x001C0000)
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 5f1fbe97aa..e88c10eea1 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -75,6 +75,9 @@ const char *soc_acpi_name(const struct device *dev)
 	switch (dev->path.pci.devfn) {
 	case SA_DEVFN_ROOT:		return "MCHC";
 	case SA_DEVFN_CPU_PCIE:		return "PEG0";
+	case SA_DEVFN_PEG1:		return "PEG1";
+	case SA_DEVFN_PEG2:		return "PEG2";
+	case SA_DEVFN_PEG3:		return "PEG3";
 	case SA_DEVFN_TCSS_XDCI:	return "TXDC";
 	case SA_DEVFN_TBT0:		return "TRP0";
 	case SA_DEVFN_TBT1:		return "TRP1";
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index f438c7a084..82936b1f31 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -22,6 +22,11 @@
 #define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 #endif
 
+#define SA_DEV_SLOT_PEG		0x01
+#define  SA_DEVFN_PEG1		PCI_DEVFN(SA_DEV_SLOT_PEG, 0)
+#define  SA_DEVFN_PEG2		PCI_DEVFN(SA_DEV_SLOT_PEG, 1)
+#define  SA_DEVFN_PEG3		PCI_DEVFN(SA_DEV_SLOT_PEG, 2)
+
 #define SA_DEV_SLOT_IGD		0x02
 #define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
 #define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index ec004faf85..0b7eaf9282 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -209,8 +209,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
 
 	/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
+	m_cfg->CpuPcieRpEnableMask = 0;
 	dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
-	m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
+	if (is_dev_enabled(dev)) {
+		m_cfg->CpuPcieRpEnableMask |= (1 << 0);
+	}
+	dev = pcidev_path_on_root(SA_DEVFN_PEG1);
+	if (is_dev_enabled(dev)) {
+		m_cfg->CpuPcieRpEnableMask |= (1 << 1);
+	}
+	dev = pcidev_path_on_root(SA_DEVFN_PEG2);
+	if (is_dev_enabled(dev)) {
+		m_cfg->CpuPcieRpEnableMask |= (1 << 2);
+	}
+	dev = pcidev_path_on_root(SA_DEVFN_PEG3);
+	if (is_dev_enabled(dev)) {
+		m_cfg->CpuPcieRpEnableMask |= (1 << 3);
+	}
 
 	/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
 	m_cfg->TmeEnable = CONFIG(INTEL_TME);