diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 55fedd3cf5..c4f4e50cd2 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -28,6 +28,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/xdci.h>
+#include <intelblocks/p2sb.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
@@ -175,6 +176,13 @@ void soc_init_pre_device(void *chip_info)
 	/* Perform silicon specific init. */
 	fsp_silicon_init(romstage_handoff_is_resume());
 
+	/*
+	 * Keep the P2SB device visible so it and the other devices are
+	 * visible in coreboot for driver support and PCI resource allocation.
+	 * There is no UPD setting for this.
+	 */
+	p2sb_unhide();
+
 	/* Restore GPIO IRQ polarities back to previous settings. */
 	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 0d6f7370a5..4cc9c8362b 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -46,14 +46,6 @@
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS	(1 << 8)
 
-static void disable_sideband_access(void)
-{
-	p2sb_disable_sideband_access();
-
-	/* hide p2sb device */
-	p2sb_hide();
-}
-
 static void pch_disable_heci(void)
 {
 	/* unhide p2sb device */
@@ -63,7 +55,7 @@ static void pch_disable_heci(void)
 	pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
 		PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
 
-	disable_sideband_access();
+	p2sb_disable_sideband_access();
 }
 
 static void pch_finalize_script(struct device *dev)
@@ -113,6 +105,9 @@ static void pch_finalize_script(struct device *dev)
 	/* we should disable Heci1 based on the devicetree policy */
 	if (config->HeciEnabled == 0)
 		pch_disable_heci();
+
+	/* Hide p2sb device as the OS must not change BAR0. */
+	p2sb_hide();
 }
 
 static void soc_lockdown(struct device *dev)