SMM: Fix state save map for sandybridge and TSEG
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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committed by
Ronald G. Minnich
parent
181bbdd51c
commit
51cb26d92a
@@ -117,8 +117,14 @@ void smi_handler(u32 smm_revision)
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{
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unsigned int node;
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smm_state_save_area_t state_save;
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u32 smm_base = 0xa8000; /* ASEG */
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#if !CONFIG_SMM_TSEG
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#if CONFIG_SMM_TSEG
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/* Update global variable TSEG base */
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if (!smi_get_tseg_base())
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return;
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smm_base = smi_get_tseg_base() + 0x8000;
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#else
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/* Are we ok to execute the handler? */
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if (!smi_obtain_lock()) {
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/* For security reasons we don't release the other CPUs
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@@ -146,18 +152,22 @@ void smi_handler(u32 smm_revision)
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case 0x00030007:
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state_save.type = LEGACY;
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state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
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(0xa8000 + 0x7e00 - (node * 0x400));
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(smm_base + 0x7e00 - (node * 0x400));
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break;
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case 0x00030100:
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case 0x00030101: /* SandyBridge */
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state_save.type = EM64T;
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state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
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(0xa8000 + 0x7d00 - (node * 0x400));
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(smm_base + 0x7d00 - (node * 0x400));
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case 0x00030101: /* SandyBridge/IvyBridge */
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state_save.type = EM64T101;
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state_save.em64t101_state_save =
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(em64t101_smm_state_save_area_t *)
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(smm_base + 0x7d00 - (node * 0x400));
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break;
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case 0x00030064:
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state_save.type = AMD64;
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state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
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(0xa8000 + 0x7e00 - (node * 0x400));
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(smm_base + 0x7e00 - (node * 0x400));
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break;
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default:
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printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
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