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Trivial. Re-indent the code.

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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
2010-10-01 06:27:35 +00:00
committed by Zheng Bao
parent 4292684e1a
commit 52000e1688
6 changed files with 16 additions and 16 deletions
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6
src/northbridge/amd/amdmct/mct/mctchi_d.c
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@@ -65,9 +65,9 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
DramBase = pDCTstat->NodeSysBase >> 8; DramBase = pDCTstat->NodeSysBase >> 8;
dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8; dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114); dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
if (dct0_size >= 0x10000) { if (dct0_size >= 0x10000) {
dct0_size -= HoleSize; dct0_size -= HoleSize;
} }
dct0_size -= DramBase; dct0_size -= DramBase;
dct1_size -= dct0_size; dct1_size -= dct0_size;

6
src/northbridge/amd/amdmct/mct/mctsrc.c
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@@ -961,7 +961,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
val += val0; val += val0;
} }
pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
} }
} }
SetEccDQSRcvrEn_D(pDCTstat, Channel); SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -979,8 +979,8 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
if (!pDCTstat->NodePresent) if (!pDCTstat->NodePresent)
break; break;
if (pDCTstat->DCTSysLimit) { if (pDCTstat->DCTSysLimit) {
for(i=0; i<2; i++) for(i=0; i<2; i++)
CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
} }
} }
} }

4
src/northbridge/amd/amdmct/mct/mcttmrl.c
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@@ -220,8 +220,8 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) { if (pDCTstat->GangedMode) {
Channel = 0; // for safe Channel = 0; // for safe
for (i=0; i<2; i++) for (i=0; i<2; i++)
pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
} else { } else {
pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
} }

6
src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
View File

@@ -61,9 +61,9 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
DramBase = pDCTstat->NodeSysBase >> 8; DramBase = pDCTstat->NodeSysBase >> 8;
dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8; dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114); dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
if (dct0_size >= 0x10000) { if (dct0_size >= 0x10000) {
dct0_size -= HoleSize; dct0_size -= HoleSize;
} }
dct0_size -= DramBase; dct0_size -= DramBase;
dct1_size -= dct0_size; dct1_size -= dct0_size;

6
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@@ -914,7 +914,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
val += val1; val += val1;
} }
pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val; pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
} }
} }
SetEccDQSRcvrEn_D(pDCTstat, Channel); SetEccDQSRcvrEn_D(pDCTstat, Channel);
@@ -932,8 +932,8 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
if (!pDCTstat->NodePresent) if (!pDCTstat->NodePresent)
break; break;
if (pDCTstat->DCTSysLimit) { if (pDCTstat->DCTSysLimit) {
for(i=0; i<2; i++) for(i=0; i<2; i++)
CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
} }
} }
} }

4
src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
View File

@@ -213,8 +213,8 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) { if (pDCTstat->GangedMode) {
Channel = 0; /* for safe */ Channel = 0; /* for safe */
for (i=0; i<2; i++) for (i=0; i<2; i++)
pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
} else { } else {
pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
} }