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AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK

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Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-12-15 21:37:48 +02:00
committed by Patrick Georgi
parent b9bd69e70e
commit 520717dff1
19 changed files with 21 additions and 240 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/cpu/amd/agesa/family14/fixme.c
View File

@@ -61,25 +61,6 @@ void amd_initcpuio(void)
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}
void amd_initenv(void)
{
AMD_INTERFACE_PARAMS AmdParamStruct;

19
src/cpu/amd/agesa/family15tn/fixme.c
View File

@@ -60,22 +60,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}

19
src/cpu/amd/agesa/family16kb/fixme.c
View File

@@ -60,22 +60,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}

21
src/cpu/amd/pi/00630F01/fixme.c
View File

@@ -65,24 +65,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
* Set the MMIO Configuration Base Address
* and Bus Range onto MMIO configuration base
* Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}

28
src/cpu/amd/pi/00660F01/fixme.c
View File

@@ -64,31 +64,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
* Set the MMIO Configuration Base Address and
* Bus Range onto MMIO configuration base
* Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}

33
src/cpu/amd/pi/00730F01/fixme.c
View File

@@ -64,36 +64,3 @@ void amd_initcpuio(void)
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
void amd_initmmio(void)
{
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
* Set the MMIO Configuration Base Address and
* Bus Range onto MMIO configuration base
* Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* PSP */
//PciData = 0xD;
//PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x8, 0x0, 0x48);
//LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}