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AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK

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Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-12-15 21:37:48 +02:00
committed by Patrick Georgi
parent b9bd69e70e
commit 520717dff1
19 changed files with 21 additions and 240 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/southbridge/amd/agesa/hudson/Kconfig
View File

@@ -31,10 +31,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/agesa/hudson/bootblock.c"
config EHCI_BAR
hex
default 0xfef00000

2
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@@ -16,11 +16,9 @@ ramstage-y += sd.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock.c
bootblock-y += early_setup.c
bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
endif
romstage-y += enable_usbdebug.c
ramstage-y += enable_usbdebug.c

21
src/southbridge/amd/agesa/hudson/bootblock.c
View File

@@ -14,7 +14,10 @@
*/
#include <stdint.h>
#include <arch/bootblock.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_ops.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -56,24 +59,12 @@ static void hudson_enable_rom(void)
pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)
{
hudson_enable_rom();
}
#if !CONFIG(ROMCC_BOOTBLOCK)
#include <bootblock_common.h>
#include <amdblocks/acpimmio.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
void bootblock_soc_early_init(void)
void bootblock_early_southbridge_init(void)
{
pci_devfn_t dev;
u32 data;
bootblock_southbridge_init();
hudson_enable_rom();
enable_acpimmio_decode_pm24();
hudson_lpc_decode();
@@ -94,7 +85,6 @@ void bootblock_soc_early_init(void)
* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
* 0x7e and 0xef-0xee.
*/
data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
data |= TPM_12_EN | TPM_LEGACY_EN;
pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
@@ -109,4 +99,3 @@ void bootblock_soc_early_init(void)
*/
pm_write8(0xd2, 0);
}
#endif

2
src/southbridge/amd/cimx/sb800/Makefile.inc
View File

@@ -16,9 +16,7 @@
# SB800 Platform Files
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock.c
endif
romstage-y += cfg.c
romstage-y += early.c

25
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@@ -13,7 +13,8 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <amdblocks/acpimmio.h>
#include <arch/bootblock.h>
#include <device/pci_ops.h>
static void enable_rom(void)
@@ -79,17 +80,6 @@ static void enable_spi_fast_mode(void)
pci_io_write_config32(dev, 0xa0, save);
}
static void enable_acpimmio_decode_pm24(void)
{
u8 reg8;
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
}
static void enable_clocks(void)
{
u32 reg32;
@@ -109,7 +99,7 @@ static void enable_clocks(void)
*acpi_mmio = reg32;
}
static void bootblock_southbridge_init(void)
void bootblock_early_southbridge_init(void)
{
/* Setup the ROM access for 2M */
enable_rom();
@@ -120,12 +110,3 @@ static void bootblock_southbridge_init(void)
enable_acpimmio_decode_pm24();
enable_clocks();
}
#if !CONFIG(ROMCC_BOOTBLOCK)
#include <bootblock_common.h>
void bootblock_soc_early_init(void)
{
bootblock_southbridge_init();
}
#endif

4
src/southbridge/amd/pi/hudson/Kconfig
View File

@@ -34,10 +34,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/pi/hudson/bootblock.c"
config EHCI_BAR
hex
default 0xfef00000

2
src/southbridge/amd/pi/hudson/Makefile.inc
View File

@@ -28,11 +28,9 @@
#
#*****************************************************************************
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock.c
bootblock-y += early_setup.c
bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
endif
romstage-y += early_setup.c
romstage-y += enable_usbdebug.c

19
src/southbridge/amd/pi/hudson/bootblock.c
View File

@@ -14,7 +14,10 @@
*/
#include <stdint.h>
#include <arch/bootblock.h>
#include <amdblocks/acpimmio.h>
#include <device/pci_ops.h>
#include <southbridge/amd/pi/hudson/hudson.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -56,23 +59,12 @@ static void hudson_enable_rom(void)
pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)
{
hudson_enable_rom();
}
#if !CONFIG(ROMCC_BOOTBLOCK)
#include <bootblock_common.h>
#include <amdblocks/acpimmio.h>
#include <southbridge/amd/pi/hudson/hudson.h>
void bootblock_soc_early_init(void)
void bootblock_early_southbridge_init(void)
{
pci_devfn_t dev;
u32 data;
bootblock_southbridge_init();
hudson_enable_rom();
if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON))
enable_acpimmio_decode_pm24();
else
@@ -111,4 +103,3 @@ void bootblock_soc_early_init(void)
*/
pm_write8(0xd2, 0);
}
#endif