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vc/intel/raptorlake: Update header files from 4301_01 to 4435_00

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Update header files for FSP for Raptor Lake platform to version 4435_00,
previous version being 4301_01.

FSPM:
1. Options changed for Ppr Enable
2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's

FSPS:
1. Add 'CpuPcieRpTestForceLtrOverride' UPD

MemInfoHob:
1. Structure updated

BUG=b:315234533
Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=793230

Cq-Depend: chrome-internal:6786881, chrome-internal:6787635
Cq-Depend: chrome-internal:6719974, chromium:5125983
Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Kulkarni, Srinivas
2023-12-16 10:00:57 +05:30
committed by Martin L Roth
parent 224098dffd
commit 520ca9a518
3 changed files with 14 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h
View File

@@ -3754,8 +3754,8 @@ typedef struct {
UINT32 SerialIoUartDebugCtsPinMux; UINT32 SerialIoUartDebugCtsPinMux;
/** Offset 0x0AA8 - Ppr Enable Type /** Offset 0x0AA8 - Ppr Enable Type
Enable Soft or Hard PPR <b>0:Disable</b>, 2:Hard PPR Enable Soft or Hard PPR 0:Disable, 1:Soft PPR, <b>2:Hard PPR</b>, 3:No Repair
0:Disable, 2:Hard PPR 0:Disable, 1:Soft PPR, 2:Hard PPR, 3:No Repair
**/ **/
UINT8 PprEnable; UINT8 PprEnable;
@@ -3795,8 +3795,16 @@ typedef struct {
UINT8 CpuPcieRpSlotImplemented[4]; UINT8 CpuPcieRpSlotImplemented[4];
/** Offset 0x0AB6 /** Offset 0x0AB6
Enable PPR Run Once 0:Disable, <b>1:Enable<b>
0:Disable, 1:Enable
**/ **/
UINT8 Rsvd28[2]; UINT8 PprRunOnce;
/** Offset 0x0AB7 - Post Package Repair
Enables/Disable Post Package Repair
$EN_DIS
**/
UINT8 PPR;
/** Offset 0x0AB8 - IbeccErrInjAddress /** Offset 0x0AB8 - IbeccErrInjAddress
Address to match against for ECC error injection Address to match against for ECC error injection

2
src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h
View File

@@ -4296,7 +4296,7 @@ typedef struct {
/** Offset 0x104C /** Offset 0x104C
**/ **/
UINT8 Rsvd39[4]; UINT8 CpuPcieRpTestForceLtrOverride[4];
/** Offset 0x1050 - MemoryBuffer /** Offset 0x1050 - MemoryBuffer
MemoryBuffer address MemoryBuffer address

2
src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h
View File

@@ -281,6 +281,8 @@ typedef struct {
BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows.
UINT16 PprRepairFails; ///< PPR: Counts of repair failure.
} MEMORY_INFO_DATA_HOB; } MEMORY_INFO_DATA_HOB;
/** /**