Add a few missing license headers based on svn logs, and also add a

few more code comments to src/cpu/x86/*.inc files.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/x86/fpu_enable.inc

@@ -1,10 +1,39 @@
-	/* preserve BIST in %eax */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 __fpu_start:
+	/* Preserve BIST. */
 	movl	%eax, %ebp
 
-	/* Disable floating point emulation */
+	/*
+	 * Clear the CR0[2] bit (the "Emulation" flag, EM).
+	 *
+	 * This indicates that the processor has an (internal or external)
+	 * x87 FPU, i.e. floating point operations will be executed by the
+	 * hardware (and not emulated in software).
+	 *
+	 * Additionally, if this bit is not cleared, MMX/SSE instructions won't
+	 * work, i.e., they will trigger an invalid opcode exception (#UD).
+	 */
 	movl	%cr0, %eax
-	andl	$~(1<<2), %eax
+	andl	$~(1 << 2), %eax
 	movl	%eax, %cr0
 
+	/* Restore BIST. */
 	movl	%ebp, %eax

src/cpu/x86/mmx_disable.inc

@@ -1,2 +1,24 @@
-	/* Clear out an mmx state */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+	/*
+	 * Execute the EMMS (Empty MMX Technology State) instruction.
+	 */
 	emms
+

src/cpu/x86/sse_disable.inc

@@ -1,8 +1,26 @@
-	/*
+/*
-	 * Put the processor back into a reset state
+ * This file is part of the coreboot project.
-	 * with respect to the xmm registers.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+	/*
+	 * Put the processor back into a reset state
+	 * with respect to the XMM registers.
+	 */
 	xorps %xmm0, %xmm0
 	xorps %xmm1, %xmm1
 	xorps %xmm2, %xmm2
@@ -12,7 +30,15 @@
 	xorps %xmm6, %xmm6
 	xorps %xmm7, %xmm7
 
-	/* Disable sse instructions */
+	/*
+	 * Disable SSE instructions.
+	 *
+	 * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the
+	 * processor can no longer execute SSE instructions, and unmasked
+	 * SIMD floating point exceptions will generate an invalid opcode
+	 * exception (#UD).
+	 */
 	movl	%cr4, %eax
-	andl	$~(3<<9), %eax
+	andl	$~(3 << 9), %eax
 	movl	%eax, %cr4
+

src/cpu/x86/sse_enable.inc

@@ -1,14 +1,30 @@
-	/* preserve BIST in %eax */
+/*
-	movl %eax, %ebp
+ * This file is part of the coreboot project.
-
+ *
-	/*
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
-	 * Enable the use of the xmm registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/* Enable sse instructions */
+	/* Preserve BIST. */
+	movl	%eax, %ebp
+
+	/* Enable SSE instructions. */
 	movl	%cr4, %eax
-	orl	$(1<<9), %eax
+	orl	$(1 << 9), %eax
 	movl	%eax, %cr4
 
+	/* Restore BIST. */
 	movl	%ebp, %eax