soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions

- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.

- Add gpio pin definitions for CNP-H and related changes.

- Add gpio device name, host software ownership reg offset for CNP-H.

BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
      RVP11 and verify power management, IO device functionalities
      work fine.

Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/cannonlake/Kconfig

@@ -10,7 +10,7 @@ config SOC_INTEL_COFFEELAKE
 	help
 	  Intel Coffeelake support
 
-config CANNONLAKE_SOC_PCH_H
+config SOC_INTEL_CANNONLAKE_PCH_H
 	bool
 	default n
 	help
@@ -165,7 +165,7 @@ config NHLT_DA7219
 
 config MAX_ROOT_PORTS
 	int
-	default 24 if CANNONLAKE_SOC_PCH_H
+	default 24 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 16
 
 config SMM_TSEG_SIZE
@@ -204,7 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 
 config SOC_INTEL_I2C_DEV_MAX
 	int
-	default 4 if CANNONLAKE_SOC_PCH_H
+	default 4 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 6
 
 # Clock divider parameters for 115200 baud rate