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Fix Fam14 mainboard whitespace

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Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes

Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Marc Jones
2012-01-03 16:02:07 -07:00
parent 8bd41cd3b5
commit 522ba28874
10 changed files with 2228 additions and 2232 deletions
Download Patch File Download Diff File Expand all files Collapse all files

304
src/mainboard/amd/inagua/acpi_tables.c
View File

@@ -38,15 +38,15 @@ extern u32 apicid_sb800;
static void dump_mem(u32 start, u32 end) static void dump_mem(u32 start, u32 end)
{ {
u32 i; u32 i;
print_debug("dump_mem:"); print_debug("dump_mem:");
for (i = start; i < end; i++) { for (i = start; i < end; i++) {
if ((i & 0xf) == 0) { if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, "\n%08x:", i);
} }
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
} }
print_debug("\n"); print_debug("\n");
} }
#endif #endif
@@ -56,197 +56,197 @@ extern const unsigned char AmlCode_ssdt[];
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
/* Just a dummy */ /* Just a dummy */
return current; return current;
} }
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0); current, 0, 0, 2, 0);
/* 0: mean bus 0--->ISA */ /* 0: mean bus 0--->ISA */
/* 0: PIC 0 */ /* 0: PIC 0 */
/* 2: APIC 2 */ /* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */ /* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
/* 1: LINT1 connect to NMI */ /* 1: LINT1 connect to NMI */
return current; return current;
} }
unsigned long acpi_fill_slit(unsigned long current) unsigned long acpi_fill_slit(unsigned long current)
{ {
// Not implemented // Not implemented
return current; return current;
} }
unsigned long acpi_fill_srat(unsigned long current) unsigned long acpi_fill_srat(unsigned long current)
{ {
/* No NUMA, no SRAT */ /* No NUMA, no SRAT */
return current; return current;
} }
unsigned long write_acpi_tables(unsigned long start) unsigned long write_acpi_tables(unsigned long start)
{ {
unsigned long current; unsigned long current;
acpi_rsdp_t *rsdp; acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt; acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet; acpi_hpet_t *hpet;
acpi_madt_t *madt; acpi_madt_t *madt;
acpi_srat_t *srat; acpi_srat_t *srat;
acpi_slit_t *slit; acpi_slit_t *slit;
acpi_fadt_t *fadt; acpi_fadt_t *fadt;
acpi_facs_t *facs; acpi_facs_t *facs;
acpi_header_t *dsdt; acpi_header_t *dsdt;
acpi_header_t *ssdt; acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */ /* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10; start = (start + 0x0f) & -0x10;
current = start; current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */ /* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current; rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t); current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current; rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t); current += sizeof(acpi_rsdt_t);
/* clear all table memory */ /* clear all table memory */
memset((void *)start, 0, current - start); memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt); acpi_write_rsdt(rsdt);
/* DSDT */ /* DSDT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length; current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length); memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment /* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t); current += sizeof(acpi_facs_t);
acpi_create_facs(facs); acpi_create_facs(facs);
/* FADT */ /* FADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t); current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt); acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt); acpi_add_table(rsdp, fadt);
/* /*
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
#if 0 // Don't need HPET table. #if 0 // Don't need HPET table.
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t); current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet); acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet); acpi_add_table(rsdp, hpet);
#endif #endif
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current; madt = (acpi_madt_t *) current;
acpi_create_madt(madt); acpi_create_madt(madt);
current += madt->header.length; current += madt->header.length;
acpi_add_table(rsdp, madt); acpi_add_table(rsdp, madt);
/* SRAT */ /* SRAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) { if (srat != NULL) {
memcpy(current, srat, srat->header.length); memcpy(current, srat, srat->header.length);
srat = (acpi_srat_t *) current; srat = (acpi_srat_t *) current;
//acpi_create_srat(srat); //acpi_create_srat(srat);
current += srat->header.length; current += srat->header.length;
acpi_add_table(rsdp, srat); acpi_add_table(rsdp, srat);
} }
/* SLIT */ /* SLIT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) { if (slit != NULL) {
memcpy(current, slit, slit->header.length); memcpy(current, slit, slit->header.length);
slit = (acpi_slit_t *) current; slit = (acpi_slit_t *) current;
//acpi_create_slit(slit); //acpi_create_slit(slit);
current += slit->header.length; current += slit->header.length;
acpi_add_table(rsdp, slit); acpi_add_table(rsdp, slit);
} }
/* SSDT */ /* SSDT */
current = ( current + 0x0f) & -0x10; current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) { if (ssdt != NULL) {
memcpy(current, ssdt, ssdt->length); memcpy(current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
current += ssdt->length; current += ssdt->length;
} }
else { else {
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length; current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length); memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
/* recalculate checksum */ /* recalculate checksum */
ssdt->checksum = 0; ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
#if DUMP_ACPI_TABLES == 1 #if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n"); printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n"); printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n"); printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length); dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n"); printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length); dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n"); printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length); dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n"); printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n"); printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length); dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif #endif
printk(BIOS_INFO, "ACPI: done.\n"); printk(BIOS_INFO, "ACPI: done.\n");
return current; return current;
} }

755
src/mainboard/amd/inagua/agesawrapper.c
View File

@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/*---------------------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* M O D U L E S U S E D * M O D U L E S U S E D
*---------------------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*/ */
#include <stdint.h> #include <stdint.h>
@@ -39,503 +39,498 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S * D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*--------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S * L O C A L F U N C T I O N S
*--------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00000B00; PciData = 0x00000B00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = 0x00000A03; PciData = 0x00000A03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set TOM-DFFFFFFF to Node0 Link0. */ /* Set TOM-DFFFFFFF to Node0 Link0. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00DFFF00; PciData = 0x00DFFF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
PciData = 0x00FFFF00 | 0x80; PciData = 0x00FFFF00 | 0x80;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
PciData = (PCIE_BASE_ADDRESS >> 8) | 03; PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000; PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000013; PciData = 0x00000013;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitmmio ( agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register. Address MSR register.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/* /*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/ */
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000; MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */ /* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002; PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitreset ( agesawrapper_amdinitreset (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader)); &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost; AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams; AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitearly ( agesawrapper_amdinitearly (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr); OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitpost ( agesawrapper_amdinitpost (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
UINT32 *HeadPtr; UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{ {
*HeadPtr = 0x00000000; *HeadPtr = 0x00000000;
HeadPtr++; HeadPtr++;
} }
BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitenv ( agesawrapper_amdinitenv (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */ /* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100; PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address /* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20 * Modify B0D1F0x20
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20; PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600; PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base /* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24 * Modify B0D1F0x24
*/ */
PciAddress.Address.Register = 0x24; PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001; PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
VOID * VOID *
agesawrapper_getlateinitptr ( agesawrapper_getlateinitptr (
int pick int pick
) )
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
return DmiTable; return DmiTable;
case PICK_PSTATE:
case PICK_PSTATE: return AcpiPstate;
return AcpiPstate; case PICK_SRAT:
return AcpiSrat;
case PICK_SRAT: case PICK_SLIT:
return AcpiSrat; return AcpiSlit;
case PICK_WHEA_MCE:
case PICK_SLIT: return AcpiWheaMce;
return AcpiSlit; case PICK_WHEA_CMC:
case PICK_WHEA_MCE: return AcpiWheaCmc;
return AcpiWheaMce; case PICK_ALIB:
case PICK_WHEA_CMC: return AcpiAlib;
return AcpiWheaCmc; default:
case PICK_ALIB: return NULL;
return AcpiAlib; }
default:
return NULL;
}
} }
UINT32 UINT32
agesawrapper_amdinitmid ( agesawrapper_amdinitmid (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitlate ( agesawrapper_amdinitlate (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0; AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdInitLate (&AmdLateParams); Status = AmdInitLate (&AmdLateParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; return (UINT32)Status;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdlaterunaptask ( agesawrapper_amdlaterunaptask (
UINT32 Data, UINT32 Data,
VOID *ConfigPtr VOID *ConfigPtr
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0; AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdLateRunApTask (&AmdLateParams); Status = AmdLateRunApTask (&AmdLateParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; return (UINT32)Status;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdreadeventlog ( agesawrapper_amdreadeventlog (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
} }
return (UINT32)Status; return (UINT32)Status;
} }

44
src/mainboard/amd/persimmon/acpi_tables.c
View File

@@ -9,12 +9,12 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <console/console.h> #include <console/console.h>
@@ -130,23 +130,23 @@ unsigned long write_acpi_tables(unsigned long start)
/* DSDT */ /* DSDT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length; current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length); memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment /* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t); current += sizeof(acpi_facs_t);
acpi_create_facs(facs); acpi_create_facs(facs);
/* FDAT */ /* FDAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t); current += sizeof(acpi_fadt_t);
@@ -157,7 +157,7 @@ unsigned long write_acpi_tables(unsigned long start)
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t); current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet); acpi_create_hpet(hpet);
@@ -165,7 +165,7 @@ unsigned long write_acpi_tables(unsigned long start)
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current; madt = (acpi_madt_t *) current;
acpi_create_madt(madt); acpi_create_madt(madt);
current += madt->header.length; current += madt->header.length;
@@ -173,31 +173,31 @@ unsigned long write_acpi_tables(unsigned long start)
/* SRAT */ /* SRAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) { if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length); memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current; srat = (acpi_srat_t *) current;
//acpi_create_srat(srat); //acpi_create_srat(srat);
current += srat->header.length; current += srat->header.length;
acpi_add_table(rsdp, srat); acpi_add_table(rsdp, srat);
} }
/* SLIT */ /* SLIT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) { if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length); memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current; slit = (acpi_slit_t *) current;
//acpi_create_slit(slit); //acpi_create_slit(slit);
current += slit->header.length; current += slit->header.length;
acpi_add_table(rsdp, slit); acpi_add_table(rsdp, slit);
} }
/* SSDT */ /* SSDT */
current = ( current + 0x0f) & -0x10; current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) { if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length); memcpy((void *)current, ssdt, ssdt->length);
@@ -215,7 +215,7 @@ unsigned long write_acpi_tables(unsigned long start)
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
#if DUMP_ACPI_TABLES == 1 #if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n"); printk(BIOS_DEBUG, "rsdp\n");

159
src/mainboard/amd/persimmon/agesawrapper.c
View File

@@ -9,17 +9,17 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/*---------------------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* M O D U L E S U S E D * M O D U L E S U S E D
*---------------------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*/ */
#include <stdint.h> #include <stdint.h>
@@ -40,52 +40,52 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S * D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
#define MMCONF_ENABLE 1 #define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*--------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S * L O C A L F U N C T I O N S
*--------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
@@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio (
*/ */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
@@ -130,15 +130,15 @@ agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0; UINT8 BusRangeVal = 0;
UINT8 BusNum; UINT8 BusNum;
UINT8 Index; UINT8 Index;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
@@ -185,14 +185,14 @@ agesawrapper_amdinitreset (
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader)); &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost; AmdParamStruct.AllocationMethod = ByHost;
@@ -218,12 +218,12 @@ agesawrapper_amdinitearly (
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -250,14 +250,14 @@ agesawrapper_amdinitpost (
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
UINT32 *HeadPtr; UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -275,7 +275,8 @@ agesawrapper_amdinitpost (
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{
*HeadPtr = 0x00000000; *HeadPtr = 0x00000000;
HeadPtr++; HeadPtr++;
} }
@@ -296,9 +297,9 @@ agesawrapper_amdinitenv (
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
@@ -311,7 +312,7 @@ agesawrapper_amdinitenv (
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
@@ -423,9 +424,9 @@ agesawrapper_amdinitmid (
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
@@ -452,9 +453,9 @@ agesawrapper_amdinitlate (
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -467,14 +468,14 @@ agesawrapper_amdinitlate (
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib; AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status; return (UINT32)Status;
} }
@@ -490,9 +491,9 @@ agesawrapper_amdlaterunaptask (
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, LibAmdMemFill (&ApExeParams,
0, 0,
sizeof (AP_EXE_PARAMS), sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader)); &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -520,9 +521,9 @@ agesawrapper_amdreadeventlog (
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;

310
src/mainboard/amd/south_station/acpi_tables.c
View File

@@ -35,15 +35,15 @@
static void dump_mem(u32 start, u32 end) static void dump_mem(u32 start, u32 end)
{ {
u32 i; u32 i;
print_debug("dump_mem:"); print_debug("dump_mem:");
for (i = start; i < end; i++) { for (i = start; i < end; i++) {
if ((i & 0xf) == 0) { if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, "\n%08x:", i);
} }
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
} }
print_debug("\n"); print_debug("\n");
} }
#endif #endif
@@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[];
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
/* Just a dummy */ /* Just a dummy */
return current; return current;
} }
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0); current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF); current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */ /* 0: mean bus 0--->ISA */
/* 0: PIC 0 */ /* 0: PIC 0 */
/* 2: APIC 2 */ /* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */ /* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */ /* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */ /* 1: LINT1 connect to NMI */
return current; return current;
} }
unsigned long acpi_fill_slit(unsigned long current) unsigned long acpi_fill_slit(unsigned long current)
{ {
// Not implemented // Not implemented
return current; return current;
} }
unsigned long acpi_fill_srat(unsigned long current) unsigned long acpi_fill_srat(unsigned long current)
{ {
/* No NUMA, no SRAT */ /* No NUMA, no SRAT */
return current; return current;
} }
unsigned long write_acpi_tables(unsigned long start) unsigned long write_acpi_tables(unsigned long start)
{ {
unsigned long current; unsigned long current;
acpi_rsdp_t *rsdp; acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt; acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet; acpi_hpet_t *hpet;
acpi_madt_t *madt; acpi_madt_t *madt;
acpi_srat_t *srat; acpi_srat_t *srat;
acpi_slit_t *slit; acpi_slit_t *slit;
acpi_fadt_t *fadt; acpi_fadt_t *fadt;
acpi_facs_t *facs; acpi_facs_t *facs;
acpi_header_t *dsdt; acpi_header_t *dsdt;
acpi_header_t *ssdt; acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */ /* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10; start = (start + 0x0f) & -0x10;
current = start; current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */ /* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current; rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t); current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current; rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t); current += sizeof(acpi_rsdt_t);
/* clear all table memory */ /* clear all table memory */
memset((void *)start, 0, current - start); memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt); acpi_write_rsdt(rsdt);
/* DSDT */ /* DSDT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length; current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length); memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment /* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t); current += sizeof(acpi_facs_t);
acpi_create_facs(facs); acpi_create_facs(facs);
/* FDAT */ /* FDAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t); current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt); acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt); acpi_add_table(rsdp, fadt);
/* /*
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t); current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet); acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet); acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current; madt = (acpi_madt_t *) current;
acpi_create_madt(madt); acpi_create_madt(madt);
current += madt->header.length; current += madt->header.length;
acpi_add_table(rsdp, madt); acpi_add_table(rsdp, madt);
/* SRAT */ /* SRAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) { if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length); memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current; srat = (acpi_srat_t *) current;
//acpi_create_srat(srat); //acpi_create_srat(srat);
current += srat->header.length; current += srat->header.length;
acpi_add_table(rsdp, srat); acpi_add_table(rsdp, srat);
} }
/* SLIT */ /* SLIT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) { if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length); memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current; slit = (acpi_slit_t *) current;
//acpi_create_slit(slit); //acpi_create_slit(slit);
current += slit->header.length; current += slit->header.length;
acpi_add_table(rsdp, slit); acpi_add_table(rsdp, slit);
} }
/* SSDT */ /* SSDT */
current = ( current + 0x0f) & -0x10; current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) { if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length); memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
current += ssdt->length; current += ssdt->length;
} }
else { else {
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length; current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length); memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
char *position = ssdt; char *position = ssdt;
if (memcmp(position + 50, "TOM1", 4) == 0) if (memcmp(position + 50, "TOM1", 4) == 0)
*(u32 *)(position + 55) = __readmsr(0xc001001a); *(u32 *)(position + 55) = __readmsr(0xc001001a);
/* recalculate checksum */ /* recalculate checksum */
ssdt->checksum = 0; ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
#if DUMP_ACPI_TABLES == 1 #if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n"); printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n"); printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n"); printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length); dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n"); printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length); dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n"); printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length); dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n"); printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n"); printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length); dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif #endif
printk(BIOS_INFO, "ACPI: done.\n"); printk(BIOS_INFO, "ACPI: done.\n");
return current; return current;
} }

764
src/mainboard/amd/south_station/agesawrapper.c
View File

@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/*---------------------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* M O D U L E S U S E D * M O D U L E S U S E D
*---------------------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*/ */
#include <stdint.h> #include <stdint.h>
@@ -40,502 +40,502 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S * D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
#define MMCONF_ENABLE 1 #define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*--------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S * L O C A L F U N C T I O N S
*--------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* Enable legacy video routing: D18F1xF4 VGA Enable */
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
* set to non-posted regions. PciData = 1;
*/ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
PciData |= 1 << 7; // set NP (non-posted) bit * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); * set to non-posted regions.
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); */
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
/* Map the remaining PCI hole as posted MMIO */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = 0x00FECF00; // last address before non-posted range PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; /* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = (UINT32)MsrReg; PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = 0x0000F000; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003; /* Send all IO (0000-FFFF) to southbridge. */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
Status = AGESA_SUCCESS; PciData = 0x0000F000;
return (UINT32)Status; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitmmio ( agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/* UINT8 BusRangeVal = 0;
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base UINT8 BusNum;
Address MSR register. UINT8 Index;
*/
for (Index = 0; Index < 8; Index++) { /*
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
if (BusNum == 1) { Address MSR register.
BusRangeVal = Index; */
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); for (Index = 0; Index < 8; Index++) {
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
/* MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */ /*
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
PciData = 0x01308002; */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); MsrReg = MsrReg | 0x0000400000000000ull;
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; /* Set Ontario Link Data */
return (UINT32)Status; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitreset ( agesawrapper_amdinitreset (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader)); &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost; AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams; AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitearly ( agesawrapper_amdinitearly (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr); OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitpost ( agesawrapper_amdinitpost (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
UINT32 *HeadPtr; UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{ {
*HeadPtr = 0x00000000; *HeadPtr = 0x00000000;
HeadPtr++; HeadPtr++;
} }
BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitenv ( agesawrapper_amdinitenv (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */ /* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100; PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address /* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20 * Modify B0D1F0x20
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20; PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600; PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base /* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24 * Modify B0D1F0x24
*/ */
PciAddress.Address.Register = 0x24; PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001; PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
VOID * VOID *
agesawrapper_getlateinitptr ( agesawrapper_getlateinitptr (
int pick int pick
) )
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
return DmiTable; return DmiTable;
case PICK_PSTATE: case PICK_PSTATE:
return AcpiPstate; return AcpiPstate;
case PICK_SRAT: case PICK_SRAT:
return AcpiSrat; return AcpiSrat;
case PICK_SLIT: case PICK_SLIT:
return AcpiSlit; return AcpiSlit;
case PICK_WHEA_MCE: case PICK_WHEA_MCE:
return AcpiWheaMce; return AcpiWheaMce;
case PICK_WHEA_CMC: case PICK_WHEA_CMC:
return AcpiWheaCmc; return AcpiWheaCmc;
case PICK_ALIB: case PICK_ALIB:
return AcpiAlib; return AcpiAlib;
default: default:
return NULL; return NULL;
} }
} }
UINT32 UINT32
agesawrapper_amdinitmid ( agesawrapper_amdinitmid (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitlate ( agesawrapper_amdinitlate (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0; AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdInitLate (&AmdLateParams); Status = AmdInitLate (&AmdLateParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib; AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdlaterunaptask ( agesawrapper_amdlaterunaptask (
UINT32 Func, UINT32 Func,
UINT32 Data, UINT32 Data,
VOID *ConfigPtr VOID *ConfigPtr
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, LibAmdMemFill (&ApExeParams,
0, 0,
sizeof (AP_EXE_PARAMS), sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader)); &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func; ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr; ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams); Status = AmdLateRunApTask (&ApExeParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdreadeventlog ( agesawrapper_amdreadeventlog (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
} }
return (UINT32)Status; return (UINT32)Status;
} }

310
src/mainboard/amd/union_station/acpi_tables.c
View File

@@ -35,15 +35,15 @@
static void dump_mem(u32 start, u32 end) static void dump_mem(u32 start, u32 end)
{ {
u32 i; u32 i;
print_debug("dump_mem:"); print_debug("dump_mem:");
for (i = start; i < end; i++) { for (i = start; i < end; i++) {
if ((i & 0xf) == 0) { if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, "\n%08x:", i);
} }
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
} }
print_debug("\n"); print_debug("\n");
} }
#endif #endif
@@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[];
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
/* Just a dummy */ /* Just a dummy */
return current; return current;
} }
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0); current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF); current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */ /* 0: mean bus 0--->ISA */
/* 0: PIC 0 */ /* 0: PIC 0 */
/* 2: APIC 2 */ /* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */ /* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */ /* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */ /* 1: LINT1 connect to NMI */
return current; return current;
} }
unsigned long acpi_fill_slit(unsigned long current) unsigned long acpi_fill_slit(unsigned long current)
{ {
// Not implemented // Not implemented
return current; return current;
} }
unsigned long acpi_fill_srat(unsigned long current) unsigned long acpi_fill_srat(unsigned long current)
{ {
/* No NUMA, no SRAT */ /* No NUMA, no SRAT */
return current; return current;
} }
unsigned long write_acpi_tables(unsigned long start) unsigned long write_acpi_tables(unsigned long start)
{ {
unsigned long current; unsigned long current;
acpi_rsdp_t *rsdp; acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt; acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet; acpi_hpet_t *hpet;
acpi_madt_t *madt; acpi_madt_t *madt;
acpi_srat_t *srat; acpi_srat_t *srat;
acpi_slit_t *slit; acpi_slit_t *slit;
acpi_fadt_t *fadt; acpi_fadt_t *fadt;
acpi_facs_t *facs; acpi_facs_t *facs;
acpi_header_t *dsdt; acpi_header_t *dsdt;
acpi_header_t *ssdt; acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */ /* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10; start = (start + 0x0f) & -0x10;
current = start; current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */ /* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current; rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t); current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current; rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t); current += sizeof(acpi_rsdt_t);
/* clear all table memory */ /* clear all table memory */
memset((void *)start, 0, current - start); memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt); acpi_write_rsdt(rsdt);
/* DSDT */ /* DSDT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length; current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length); memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment /* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t); current += sizeof(acpi_facs_t);
acpi_create_facs(facs); acpi_create_facs(facs);
/* FDAT */ /* FDAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t); current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt); acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt); acpi_add_table(rsdp, fadt);
/* /*
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t); current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet); acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet); acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current; madt = (acpi_madt_t *) current;
acpi_create_madt(madt); acpi_create_madt(madt);
current += madt->header.length; current += madt->header.length;
acpi_add_table(rsdp, madt); acpi_add_table(rsdp, madt);
/* SRAT */ /* SRAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) { if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length); memcpy((void *)current, srat, srat->header.length);
srat = (acpi_srat_t *) current; srat = (acpi_srat_t *) current;
//acpi_create_srat(srat); //acpi_create_srat(srat);
current += srat->header.length; current += srat->header.length;
acpi_add_table(rsdp, srat); acpi_add_table(rsdp, srat);
} }
/* SLIT */ /* SLIT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) { if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length); memcpy((void *)current, slit, slit->header.length);
slit = (acpi_slit_t *) current; slit = (acpi_slit_t *) current;
//acpi_create_slit(slit); //acpi_create_slit(slit);
current += slit->header.length; current += slit->header.length;
acpi_add_table(rsdp, slit); acpi_add_table(rsdp, slit);
} }
/* SSDT */ /* SSDT */
current = ( current + 0x0f) & -0x10; current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) { if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length); memcpy((void *)current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
current += ssdt->length; current += ssdt->length;
} }
else { else {
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length; current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length); memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
char *position = ssdt; char *position = ssdt;
if (memcmp(position + 50, "TOM1", 4) == 0) if (memcmp(position + 50, "TOM1", 4) == 0)
*(u32 *)(position + 55) = __readmsr(0xc001001a); *(u32 *)(position + 55) = __readmsr(0xc001001a);
/* recalculate checksum */ /* recalculate checksum */
ssdt->checksum = 0; ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
#if DUMP_ACPI_TABLES == 1 #if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n"); printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n"); printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n"); printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length); dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n"); printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length); dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n"); printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length); dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n"); printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n"); printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length); dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif #endif
printk(BIOS_INFO, "ACPI: done.\n"); printk(BIOS_INFO, "ACPI: done.\n");
return current; return current;
} }

764
src/mainboard/amd/union_station/agesawrapper.c
View File

@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/*---------------------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* M O D U L E S U S E D * M O D U L E S U S E D
*---------------------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*/ */
#include <stdint.h> #include <stdint.h>
@@ -40,502 +40,502 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S * D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
#define MMCONF_ENABLE 1 #define MMCONF_ENABLE 1
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S * T Y P E D E F S A N D S T R U C T U R E S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*--------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S * L O C A L F U N C T I O N S
*--------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* Enable legacy video routing: D18F1xF4 VGA Enable */
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
* set to non-posted regions. PciData = 1;
*/ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
PciData |= 1 << 7; // set NP (non-posted) bit * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); * set to non-posted regions.
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); */
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit
/* Map the remaining PCI hole as posted MMIO */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = 0x00FECF00; // last address before non-posted range PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; /* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = (UINT32)MsrReg; PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = 0x0000F000; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003; /* Send all IO (0000-FFFF) to southbridge. */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
Status = AGESA_SUCCESS; PciData = 0x0000F000;
return (UINT32)Status; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitmmio ( agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
UINT8 BusRangeVal = 0;
UINT8 BusNum;
UINT8 Index;
/* UINT8 BusRangeVal = 0;
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base UINT8 BusNum;
Address MSR register. UINT8 Index;
*/
for (Index = 0; Index < 8; Index++) { /*
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
if (BusNum == 1) { Address MSR register.
BusRangeVal = Index; */
break;
}
}
MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE); for (Index = 0; Index < 8; Index++) {
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
if (BusNum == 1) {
BusRangeVal = Index;
break;
}
}
/* MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */ /*
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
PciData = 0x01308002; */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); MsrReg = MsrReg | 0x0000400000000000ull;
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; /* Set Ontario Link Data */
return (UINT32)Status; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitreset ( agesawrapper_amdinitreset (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader)); &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost; AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams; AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitearly ( agesawrapper_amdinitearly (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr); OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitpost ( agesawrapper_amdinitpost (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
UINT32 *HeadPtr; UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */ /* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{ {
*HeadPtr = 0x00000000; *HeadPtr = 0x00000000;
HeadPtr++; HeadPtr++;
} }
BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitenv ( agesawrapper_amdinitenv (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */ /* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100; PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address /* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20 * Modify B0D1F0x20
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20; PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96009600; PciValue |= 0x96009600;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base /* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24 * Modify B0D1F0x24
*/ */
PciAddress.Address.Register = 0x24; PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001; PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
VOID * VOID *
agesawrapper_getlateinitptr ( agesawrapper_getlateinitptr (
int pick int pick
) )
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
return DmiTable; return DmiTable;
case PICK_PSTATE: case PICK_PSTATE:
return AcpiPstate; return AcpiPstate;
case PICK_SRAT: case PICK_SRAT:
return AcpiSrat; return AcpiSrat;
case PICK_SLIT: case PICK_SLIT:
return AcpiSlit; return AcpiSlit;
case PICK_WHEA_MCE: case PICK_WHEA_MCE:
return AcpiWheaMce; return AcpiWheaMce;
case PICK_WHEA_CMC: case PICK_WHEA_CMC:
return AcpiWheaCmc; return AcpiWheaCmc;
case PICK_ALIB: case PICK_ALIB:
return AcpiAlib; return AcpiAlib;
default: default:
return NULL; return NULL;
} }
} }
UINT32 UINT32
agesawrapper_amdinitmid ( agesawrapper_amdinitmid (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitlate ( agesawrapper_amdinitlate (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0; AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdInitLate (&AmdLateParams); Status = AmdInitLate (&AmdLateParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib; AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdlaterunaptask ( agesawrapper_amdlaterunaptask (
UINT32 Func, UINT32 Func,
UINT32 Data, UINT32 Data,
VOID *ConfigPtr VOID *ConfigPtr
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, LibAmdMemFill (&ApExeParams,
0, 0,
sizeof (AP_EXE_PARAMS), sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader)); &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func; ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr; ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams); Status = AmdLateRunApTask (&ApExeParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdreadeventlog ( agesawrapper_amdreadeventlog (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
} }
return (UINT32)Status; return (UINT32)Status;
} }

311
src/mainboard/asrock/e350m1/acpi_tables.c
View File

@@ -37,15 +37,15 @@
static void dump_mem(u32 start, u32 end) static void dump_mem(u32 start, u32 end)
{ {
u32 i; u32 i;
print_debug("dump_mem:"); print_debug("dump_mem:");
for (i = start; i < end; i++) { for (i = start; i < end; i++) {
if ((i & 0xf) == 0) { if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, "\n%08x:", i);
} }
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
} }
print_debug("\n"); print_debug("\n");
} }
#endif #endif
@@ -54,198 +54,199 @@ extern const unsigned char AmlCode_ssdt[];
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
/* Just a dummy */ /* Just a dummy */
return current; return current;
} }
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
IO_APIC_ADDR, 0); CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0); current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF); current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */ /* 0: mean bus 0--->ISA */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ /* 0: PIC 0 */
/* 1: LINT1 connect to NMI */ /* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
return current; /* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */
return current;
} }
unsigned long acpi_fill_slit(unsigned long current) unsigned long acpi_fill_slit(unsigned long current)
{ {
// Not implemented // Not implemented
return current; return current;
} }
unsigned long acpi_fill_srat(unsigned long current) unsigned long acpi_fill_srat(unsigned long current)
{ {
/* No NUMA, no SRAT */ /* No NUMA, no SRAT */
return current; return current;
} }
unsigned long write_acpi_tables(unsigned long start) unsigned long write_acpi_tables(unsigned long start)
{ {
unsigned long current; unsigned long current;
acpi_rsdp_t *rsdp; acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt; acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet; acpi_hpet_t *hpet;
acpi_madt_t *madt; acpi_madt_t *madt;
acpi_srat_t *srat; acpi_srat_t *srat;
acpi_slit_t *slit; acpi_slit_t *slit;
acpi_fadt_t *fadt; acpi_fadt_t *fadt;
acpi_facs_t *facs; acpi_facs_t *facs;
acpi_header_t *dsdt; acpi_header_t *dsdt;
acpi_header_t *ssdt; acpi_header_t *ssdt;
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */ /* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10; start = (start + 0x0f) & -0x10;
current = start; current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */ /* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current; rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t); current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current; rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t); current += sizeof(acpi_rsdt_t);
/* clear all table memory */ /* clear all table memory */
memset((void *)start, 0, current - start); memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt); acpi_write_rsdt(rsdt);
/* /*
* We explicitly add these tables later on: * We explicitly add these tables later on:
*/ */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current; hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t); current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet); acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet); acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */ /* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current; madt = (acpi_madt_t *) current;
acpi_create_madt(madt); acpi_create_madt(madt);
current += madt->header.length; current += madt->header.length;
acpi_add_table(rsdp, madt); acpi_add_table(rsdp, madt);
/* SRAT */ /* SRAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
if (srat != NULL) { if (srat != NULL) {
memcpy(current, srat, srat->header.length); memcpy(current, srat, srat->header.length);
srat = (acpi_srat_t *) current; srat = (acpi_srat_t *) current;
//acpi_create_srat(srat); //acpi_create_srat(srat);
current += srat->header.length; current += srat->header.length;
acpi_add_table(rsdp, srat); acpi_add_table(rsdp, srat);
} }
/* SLIT */ /* SLIT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
if (slit != NULL) { if (slit != NULL) {
memcpy(current, slit, slit->header.length); memcpy(current, slit, slit->header.length);
slit = (acpi_slit_t *) current; slit = (acpi_slit_t *) current;
//acpi_create_slit(slit); //acpi_create_slit(slit);
current += slit->header.length; current += slit->header.length;
acpi_add_table(rsdp, slit); acpi_add_table(rsdp, slit);
} }
/* SSDT */ /* SSDT */
current = ( current + 0x0f) & -0x10; current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
if (ssdt != NULL) { if (ssdt != NULL) {
memcpy(current, ssdt, ssdt->length); memcpy(current, ssdt, ssdt->length);
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
current += ssdt->length; current += ssdt->length;
} }
else { else {
ssdt = (acpi_header_t *) current; ssdt = (acpi_header_t *) current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length; current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length); memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
char *position = ssdt; char *position = ssdt;
if (memcmp (position + 50, "TOM1", 4) == 0) if (memcmp (position + 50, "TOM1", 4) == 0)
*(u32 *) (position + 55) = __readmsr (0xc001001a); *(u32 *) (position + 55) = __readmsr (0xc001001a);
/* recalculate checksum */ /* recalculate checksum */
ssdt->checksum = 0; ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
} }
acpi_add_table(rsdp,ssdt); acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
/* DSDT */ /* DSDT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length; current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length); memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment /* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t); current += sizeof(acpi_facs_t);
acpi_create_facs(facs); acpi_create_facs(facs);
/* FDAT */ /* FDAT */
current = ( current + 0x07) & -0x08; current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current; fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t); current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt); acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt); acpi_add_table(rsdp, fadt);
#if DUMP_ACPI_TABLES == 1 #if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n"); printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n"); printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n"); printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length); dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n"); printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length); dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n"); printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length); dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n"); printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length); dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n"); printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length); dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif #endif
printk(BIOS_INFO, "ACPI: done.\n"); printk(BIOS_INFO, "ACPI: done.\n");
return current; return current;
} }

739
src/mainboard/asrock/e350m1/agesawrapper.c
View File

@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/*---------------------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* M O D U L E S U S E D * M O D U L E S U S E D
*---------------------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*/ */
#include <stdint.h> #include <stdint.h>
@@ -39,490 +39,489 @@
#define FILECODE UNASSIGNED_FILE_FILECODE #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S * D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/* ACPI table pointers returned by AmdInitLate */ /* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL; VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL; VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL; VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL; VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL; VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL; VOID *AcpiAlib = NULL;
/*------------------------------------------------------------------------------
/*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S
* T Y P E D E F S A N D S T R U C T U R E S *------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S * P R O T O T Y P E S O F L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*---------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S * E X P O R T E D F U N C T I O N S
*---------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
/*--------------------------------------------------------------------------------------- /*------------------------------------------------------------------------------
* L O C A L F U N C T I O N S * L O C A L F U N C T I O N S
*--------------------------------------------------------------------------------------- *------------------------------------------------------------------------------
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1; PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions.
*/ */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
PciData |= 1 << 7; // set NP (non-posted) bit PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000; PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003; PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitmmio ( agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register. Address MSR register.
*/ */
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/* /*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/ */
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000; MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */ /* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
PciData = 0x01308002; PciData = 0x01308002;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS; Status = AGESA_SUCCESS;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdinitreset ( agesawrapper_amdinitreset (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
LibAmdMemFill (&AmdResetParams, AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
0, AmdParamStruct.AllocationMethod = ByHost;
sizeof (AMD_RESET_PARAMS), AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
&(AmdResetParams.StdHeader)); AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AmdParamStruct.AllocationMethod = ByHost; if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); AmdReleaseStruct (&AmdParamStruct);
AmdParamStruct.NewStructPtr = &AmdResetParams; return (UINT32)status;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = NULL;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitearly ( agesawrapper_amdinitearly (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr); OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitpost ( agesawrapper_amdinitpost (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
UINT32 *HeadPtr; UINT32 *HeadPtr;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); /* Initialize heap space */
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
{
*HeadPtr = 0x00000000;
HeadPtr++;
}
BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status; HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
{
*HeadPtr = 0x00000000;
HeadPtr++;
}
BiosManagerPtr->StartOfAllocatedNodes = 0;
BiosManagerPtr->StartOfFreedNodes = 0;
return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitenv ( agesawrapper_amdinitenv (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
/* Write to D1F0x18 */ /* Write to D1F0x18 */
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x00010100; PciValue |= 0x00010100;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x18; PciAddress.Address.Register = 0x18;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x96000000; PciValue |= 0x96000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20
*/
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
/* Initialize MMIO Base and Limit Address LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
* Modify B0D1F0x20 PciValue |= 0x96009600;
*/ LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0;
PciAddress.Address.Register = 0x20;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize MMIO Prefetchable Memory Limit and Base
PciValue |= 0x96009600; * Modify B0D1F0x24
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); */
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize MMIO Prefetchable Memory Limit and Base return (UINT32)status;
* Modify B0D1F0x24
*/
PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
} }
VOID * VOID *
agesawrapper_getlateinitptr ( agesawrapper_getlateinitptr (
int pick int pick
) )
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
return DmiTable; return DmiTable;
case PICK_PSTATE: case PICK_PSTATE:
return AcpiPstate; return AcpiPstate;
case PICK_SRAT: case PICK_SRAT:
return AcpiSrat; return AcpiSrat;
case PICK_SLIT: case PICK_SLIT:
return AcpiSlit; return AcpiSlit;
case PICK_WHEA_MCE: case PICK_WHEA_MCE:
return AcpiWheaMce; return AcpiWheaMce;
case PICK_WHEA_CMC: case PICK_WHEA_CMC:
return AcpiWheaCmc; return AcpiWheaCmc;
case PICK_ALIB: case PICK_ALIB:
return AcpiAlib; return AcpiAlib;
default: default:
return NULL; return NULL;
} }
} }
UINT32 UINT32
agesawrapper_amdinitmid ( agesawrapper_amdinitmid (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */ /* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitlate ( agesawrapper_amdinitlate (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_LATE_PARAMS AmdLateParams; AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, LibAmdMemFill (&AmdLateParams,
0, 0,
sizeof (AMD_LATE_PARAMS), sizeof (AMD_LATE_PARAMS),
&(AmdLateParams.StdHeader)); &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.AltImageBasePtr = 0;
AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdLateParams.StdHeader.Func = 0; AmdLateParams.StdHeader.Func = 0;
AmdLateParams.StdHeader.ImageBasePtr = 0; AmdLateParams.StdHeader.ImageBasePtr = 0;
Status = AmdInitLate (&AmdLateParams); Status = AmdInitLate (&AmdLateParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
DmiTable = AmdLateParams.DmiTable; DmiTable = AmdLateParams.DmiTable;
AcpiPstate = AmdLateParams.AcpiPState; AcpiPstate = AmdLateParams.AcpiPState;
AcpiSrat = AmdLateParams.AcpiSrat; AcpiSrat = AmdLateParams.AcpiSrat;
AcpiSlit = AmdLateParams.AcpiSlit; AcpiSlit = AmdLateParams.AcpiSlit;
AcpiWheaMce = AmdLateParams.AcpiWheaMce; AcpiWheaMce = AmdLateParams.AcpiWheaMce;
AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
AcpiAlib = AmdLateParams.AcpiAlib; AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdlaterunaptask ( agesawrapper_amdlaterunaptask (
UINT32 Func, UINT32 Func,
UINT32 Data, UINT32 Data,
VOID *ConfigPtr VOID *ConfigPtr
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, LibAmdMemFill (&ApExeParams,
0, 0,
sizeof (AP_EXE_PARAMS), sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader)); &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func; ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr; ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams); Status = AmdLateRunApTask (&ApExeParams);
if (Status != AGESA_SUCCESS) { if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(); agesawrapper_amdreadeventlog();
ASSERT(Status == AGESA_SUCCESS); ASSERT(Status == AGESA_SUCCESS);
} }
return (UINT32)Status; return (UINT32)Status;
} }
UINT32 UINT32
agesawrapper_amdreadeventlog ( agesawrapper_amdreadeventlog (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;
AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0; AmdEventParams.StdHeader.ImageBasePtr = 0;
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) { while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams); Status = AmdReadEventLog (&AmdEventParams);
} }
return (UINT32)Status; return (UINT32)Status;
} }