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- Cleanups on the romcc side including a pci interface that uses

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fewer registers, and is easier to hardcode.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-05-19 19:16:21 +00:00
parent 49cf5967ce
commit 526855741b
19 changed files with 1649 additions and 1000 deletions
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10
src/boot/hardwaremain.c
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@ -161,7 +161,7 @@ void hardwaremain(int boot_complete)
#endif
#if 1
// pick how to scan the bus. This is first so we can get at memory size.
/* pick how to scan the bus. This is first so we can get at memory size. */
printk_info("Finding PCI configuration type.\n");
pci_set_method();
post_code(0x5f);
@ -170,13 +170,15 @@ void hardwaremain(int boot_complete)
#endif
dev_enumerate();
post_code(0x66);
// Now do the real bus
// we round the total ram up a lot for thing like the SISFB, which
// shares high memory with the CPU.
/* Now do the real bus.
* We round the total ram up a lot for thing like the SISFB, which
* shares high memory with the CPU.
*/
dev_configure();
post_code(0x88);
dev_enable();
dev_initialize();
post_code(0x89);
#endif