- Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -46,12 +46,12 @@ set_var_mtrr:
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wrmsr
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write protect caching so we can do execute in place
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/* enable write back cachine so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | 0x005), %eax
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movl $(XIP_ROM_BASE | 0x006), %eax
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wrmsr
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movl $0x203, %ecx
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@ -1,7 +1,3 @@
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <console/console.h>
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#include <cpu/p5/cpuid.h>
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#ifdef i586
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@ -25,10 +25,6 @@
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* $Id$
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*/
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <console/console.h>
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#include <mem.h>
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#include <cpu/p6/msr.h>
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@ -128,8 +124,6 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
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/* setting variable mtrr, comes from linux kernel source */
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void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
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{
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unsigned int tmp;
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if (reg >= 8)
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return;
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