- Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
53
src/southbridge/amd/amd8111/amd8111_acpi.c
Normal file
53
src/southbridge/amd/amd8111/amd8111_acpi.c
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@@ -0,0 +1,53 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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static void acpi_init(struct device *dev)
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{
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uint8_t byte;
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uint16_t word;
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#if 0
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printk_debug("ACPI: disabling NMI watchdog.. ");
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pci_read_config_byte(dev, 0x49, &byte);
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pci_write_config_byte(dev, 0x49, byte | (1<<2));
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pci_read_config_byte(dev, 0x41, &byte);
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pci_write_config_byte(dev, 0x41, byte | (1<<6)|(1<<2));
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/* added from sourceforge */
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pci_read_config_byte(dev, 0x48, &byte);
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pci_write_config_byte(dev, 0x48, byte | (1<<3));
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printk_debug("done.\n");
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printk_debug("ACPI: Routing IRQ 12 to PS2 port.. ");
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pci_read_config_word(dev, 0x46, &word);
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pci_write_config_word(dev, 0x46, word | (1<<9));
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printk_debug("done.\n");
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printk_debug("ACPI: setting PM class code.. ");
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pci_write_config_dword(dev, 0x60, 0x06800000);
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printk_debug("done.\n");
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#endif
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}
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static struct device_operations acpi_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.init = acpi_init,
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.scan_bus = 0,
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};
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static struct pci_driver acpi_driver __pci_driver = {
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.ops = &acpi_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_ACPI,
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};
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65
src/southbridge/amd/amd8111/amd8111_ide.c
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65
src/southbridge/amd/amd8111/amd8111_ide.c
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@@ -0,0 +1,65 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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static void ide_init(struct device *dev)
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{
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/* Enable ide devices so the linux ide driver will work */
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uint16_t word;
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int enable_a=1, enable_b=1;
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printk_debug("ide_init\n");
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pci_read_config_word(dev, 0x40, &word);
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/* Ensure prefetch is disabled */
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word &= ~((1 << 15) | (1 << 13));
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if (enable_b) {
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/* Enable secondary ide interface */
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word |= (1<<0);
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printk_debug("IDE1 ");
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}
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if (enable_a) {
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/* Enable primary ide interface */
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word |= (1<<1);
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printk_debug("IDE0 ");
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}
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word |= (1<<12);
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word |= (1<<14);
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pci_write_config_word(dev, 0x40, word);
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word = 0x0f;
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pci_write_config_word(dev, 0x42, word);
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/* The AMD768 has a bug where the BM DMA address must be
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* 256 byte aligned while it is only 16 bytes long.
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* Hard code this to a valid address below 0x1000
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* where automatic port address assignment starts.
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* FIXME: I assume the 8111 does the same thing. We should
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* clarify. stepan@suse.de
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*/
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pci_write_config_dword(dev, 0x20, 0xf01);
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pci_write_config_dword(dev, 0x48, 0x205e5e5e);
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word = 0x06a;
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pci_write_config_word(dev, 0x4c, word);
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.init = ide_init,
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.scan_bus = 0,
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};
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static struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_IDE,
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};
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130
src/southbridge/amd/amd8111/amd8111_lpc.c
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130
src/southbridge/amd/amd8111/amd8111_lpc.c
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@@ -0,0 +1,130 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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struct ioapicreg {
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unsigned int reg;
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unsigned int value_low, value_high;
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};
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static struct ioapicreg ioapicregvalues[] = {
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#define ALL (0xff << 24)
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#define NONE (0)
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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/* mask, trigger, polarity, destination, delivery, vector */
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{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
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{0x01, DISABLED, NONE},
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{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
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{0x03, DISABLED, NONE},
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{0x04, DISABLED, NONE},
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{0x05, DISABLED, NONE},
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{0x06, DISABLED, NONE},
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{0x07, DISABLED, NONE},
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{0x08, DISABLED, NONE},
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{0x09, DISABLED, NONE},
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{0x0a, DISABLED, NONE},
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{0x0b, DISABLED, NONE},
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{0x0c, DISABLED, NONE},
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{0x0d, DISABLED, NONE},
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{0x0e, DISABLED, NONE},
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{0x0f, DISABLED, NONE},
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{0x10, DISABLED, NONE},
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{0x11, DISABLED, NONE},
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{0x12, DISABLED, NONE},
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{0x13, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x14, DISABLED, NONE},
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{0x15, DISABLED, NONE},
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{0x16, DISABLED, NONE},
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{0x17, DISABLED, NONE},
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{0x18, DISABLED, NONE},
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{0x19, DISABLED, NONE},
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{0x20, DISABLED, NONE},
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{0x21, DISABLED, NONE},
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{0x22, DISABLED, NONE},
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{0x23, DISABLED, NONE},
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};
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static void setup_ioapic(void)
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{
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int i;
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unsigned long value_low, value_high;
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unsigned long ioapic_base = 0xfec00000;
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volatile unsigned long *l;
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struct ioapicreg *a = ioapicregvalues;
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l = (unsigned long *) ioapic_base;
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for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
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i++, a++) {
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l[0] = (a->reg * 2) + 0x10;
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l[4] = a->value_low;
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value_low = l[4];
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l[0] = (a->reg *2) + 0x11;
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l[4] = a->value_high;
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value_high = l[4];
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if ((i==0) && (value_low == 0xffffffff)) {
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printk_warning("IO APIC not responding.\n");
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return;
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}
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printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
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a->reg, a->value_low, a->value_high);
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}
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}
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static void lpc_init(struct device *dev)
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{
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uint8_t byte;
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int pwr_on=-1;
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printk_debug("lpc_init\n");
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#if 0
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/* IO APIC initialization */
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pci_read_config_byte(dev, 0x4B, &byte);
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byte |= 1;
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pci_write_config_byte(dev, 0x4B, byte);
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setup_ioapic();
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#endif
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/* posted memory write enable */
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pci_read_config_byte(dev, 0x46, &byte);
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pci_write_config_byte(dev, 0x46, byte | (1<<0));
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/* power after power fail */
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pci_read_config_byte(dev, 0x43, &byte);
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if (pwr_on) {
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byte &= ~(1<<6);
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} else {
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byte |= (1<<6);
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}
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pci_write_config_byte(dev, 0x43, byte);
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}
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static struct device_operations lpc_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.init = lpc_init,
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.scan_bus = 0,
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};
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static struct pci_driver lpc_driver __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_ISA,
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};
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96
src/southbridge/amd/amd8111/amd8111_smbus.c
Normal file
96
src/southbridge/amd/amd8111/amd8111_smbus.c
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@@ -0,0 +1,96 @@
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#include <smbus.h>
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#include <pci.h>
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#include <arch/io.h>
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#define PM_BUS 0
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#define PM_DEVFN (AMD8111_DEVFN+3)
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#define SMBUS_IO_BASE 0x1000
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#define SMBHSTSTAT 0
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#define SMBHSTCTL 2
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#define SMBHSTCMD 3
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#define SMBHSTADD 4
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#define SMBHSTDAT0 5
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#define SMBHSTDAT1 6
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#define SMBBLKDAT 7
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void smbus_enable(void)
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{
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unsigned char byte;
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#if 0
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/* iobase addr */
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pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1);
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/* smbus enable */
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pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1);
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/* iospace enable */
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pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
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#endif
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/* Set PMIOEN, leaving default address 0xDD00 in 0x58 */
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byte=pcibios_read_config_byte(0,PCI_DEVFN(0x7,3), 0x41);
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pcibios_write_config_byte(0,PCI_DEVFN(0x7,3), byte | 0x80 );
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/* cont reading 207 */
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}
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void smbus_setup(void)
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{
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outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
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}
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static void smbus_wait_until_ready(void)
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{
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while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
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/* nop */
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}
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}
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static void smbus_wait_until_done(void)
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{
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unsigned char byte;
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do {
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byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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}
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while((byte &1) == 1);
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while( (byte & ~1) == 0) {
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byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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}
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}
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int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
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{
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unsigned char host_status_register;
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unsigned char byte;
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smbus_wait_until_ready();
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/* setup transaction */
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/* disable interrupts */
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
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/* set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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/* clear the data byte...*/
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outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
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/* start the command */
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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/* read results of transaction */
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byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
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*result = byte;
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return host_status_register != 0x02;
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}
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34
src/southbridge/amd/amd8111/amd8111_usb.c
Normal file
34
src/southbridge/amd/amd8111/amd8111_usb.c
Normal file
@@ -0,0 +1,34 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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static void usb_init(struct device *dev)
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{
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uint32_t cmd;
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printk_debug("USB: Setting up controller.. ");
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pci_read_config_dword(dev, PCI_COMMAND, &cmd);
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pci_write_config_dword(dev, PCI_COMMAND,
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cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
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printk_debug("done.\n");
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}
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static struct device_operations usb_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.init = usb_init,
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.scan_bus = 0,
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};
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static struct pci_driver usb_driver __pci_driver = {
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.ops = &usb_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_USB,
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};
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|
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Block a user