src/soc: Fix various typos

These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/soc/intel/apollolake/include/soc/meminit.h

@@ -76,7 +76,7 @@ enum {
  * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
  *
  * Note that the enum values correspond to the interpreted UPD fields
- * witihn Ch[3:0]_OdtConfig parameters.
+ * within Ch[3:0]_OdtConfig parameters.
 */
 enum {
 	ODT_A_B_HIGH_LOW = 0 << 1,

src/soc/intel/apollolake/meminit.c

@@ -130,10 +130,10 @@ static void enable_logical_chan0(FSP_M_CONFIG *cfg,
 	/*
 	 * CH0_DQB byte lanes in the bit swizzle configuration field are
 	 * not 1:1. The mapping within the swizzling field is:
-	 *   indicies [0:7]   - byte lane 1 (DQS1) DQ[8:15]
-	 *   indicies [8:15]  - byte lane 0 (DQS0) DQ[0:7]
-	 *   indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
-	 *   indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+	 *   indices [0:7]   - byte lane 1 (DQS1) DQ[8:15]
+	 *   indices [8:15]  - byte lane 0 (DQS0) DQ[0:7]
+	 *   indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+	 *   indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
 	 */
 	chan = &scfg->phys[LP4_PHYS_CH0B];
 	memcpy(&cfg->Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);
@@ -175,10 +175,10 @@ static void enable_logical_chan1(FSP_M_CONFIG *cfg,
 	/*
 	 * CH1_DQB byte lanes in the bit swizzle configuration field are
 	 * not 1:1. The mapping within the swizzling field is:
-	 *   indicies [0:7]   - byte lane 1 (DQS1) DQ[8:15]
-	 *   indicies [8:15]  - byte lane 0 (DQS0) DQ[0:7]
-	 *   indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
-	 *   indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+	 *   indices [0:7]   - byte lane 1 (DQS1) DQ[8:15]
+	 *   indices [8:15]  - byte lane 0 (DQS0) DQ[0:7]
+	 *   indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+	 *   indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
 	 */
 	chan = &scfg->phys[LP4_PHYS_CH1B];
 	memcpy(&cfg->Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);

src/soc/intel/apollolake/romstage.c

@@ -87,7 +87,7 @@ static void soc_early_romstage_init(void)
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 	};
 
-	/* Set Fixed MMIO addresss into PCI configuration space */
+	/* Set Fixed MMIO address into PCI configuration space */
 	sa_set_pci_bar(soc_fixed_pci_resources,
 			ARRAY_SIZE(soc_fixed_pci_resources));
 

src/soc/intel/apollolake/systemagent.c

@@ -27,7 +27,7 @@
 /*
  * SoC implementation
  *
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
  * controller.
  */
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)