arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
This commit is contained in:
Xiang Wang
Martin L Roth
parent
5787a4c53b
commit
52b81845de
@ -6,6 +6,7 @@
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#include <arch/encoding.h>
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#include <arch/smp/atomic.h>
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#include <console/console.h>
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#include <mcall.h>
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#include <vm.h>
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/* Run OpenSBI and let OpenSBI hand over control to the payload */
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@ -47,6 +48,8 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode)
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write_csr(sie, 0);
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/* disable MMU */
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write_csr(satp, 0);
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/* save stack to mscratch so trap_entry can use that as exception stack */
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write_csr(mscratch, MACHINE_STACK_TOP());
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break;
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case RISCV_PAYLOAD_MODE_M:
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status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M);
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@ -7,129 +7,129 @@
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#include <mcall.h>
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.macro restore_regs
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# restore x registers
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LOAD x1,1*REGBYTES(a0)
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LOAD x2,2*REGBYTES(a0)
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LOAD x3,3*REGBYTES(a0)
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LOAD x4,4*REGBYTES(a0)
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LOAD x5,5*REGBYTES(a0)
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LOAD x6,6*REGBYTES(a0)
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LOAD x7,7*REGBYTES(a0)
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LOAD x8,8*REGBYTES(a0)
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LOAD x9,9*REGBYTES(a0)
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LOAD x11,11*REGBYTES(a0)
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LOAD x12,12*REGBYTES(a0)
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LOAD x13,13*REGBYTES(a0)
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LOAD x14,14*REGBYTES(a0)
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LOAD x15,15*REGBYTES(a0)
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LOAD x16,16*REGBYTES(a0)
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LOAD x17,17*REGBYTES(a0)
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LOAD x18,18*REGBYTES(a0)
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LOAD x19,19*REGBYTES(a0)
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LOAD x20,20*REGBYTES(a0)
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LOAD x21,21*REGBYTES(a0)
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LOAD x22,22*REGBYTES(a0)
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LOAD x23,23*REGBYTES(a0)
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LOAD x24,24*REGBYTES(a0)
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LOAD x25,25*REGBYTES(a0)
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LOAD x26,26*REGBYTES(a0)
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LOAD x27,27*REGBYTES(a0)
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LOAD x28,28*REGBYTES(a0)
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LOAD x29,29*REGBYTES(a0)
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LOAD x30,30*REGBYTES(a0)
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LOAD x31,31*REGBYTES(a0)
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# restore a0 last
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LOAD x10,10*REGBYTES(a0)
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# restore x registers
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LOAD x1, 1 * REGBYTES(sp)
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LOAD x3, 3 * REGBYTES(sp)
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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.endm
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.endm
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.macro save_tf
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# save gprs
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STORE x1,1*REGBYTES(x2)
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STORE x3,3*REGBYTES(x2)
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STORE x4,4*REGBYTES(x2)
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STORE x5,5*REGBYTES(x2)
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STORE x6,6*REGBYTES(x2)
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STORE x7,7*REGBYTES(x2)
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STORE x8,8*REGBYTES(x2)
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STORE x9,9*REGBYTES(x2)
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STORE x10,10*REGBYTES(x2)
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STORE x11,11*REGBYTES(x2)
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STORE x12,12*REGBYTES(x2)
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STORE x13,13*REGBYTES(x2)
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STORE x14,14*REGBYTES(x2)
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STORE x15,15*REGBYTES(x2)
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STORE x16,16*REGBYTES(x2)
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STORE x17,17*REGBYTES(x2)
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STORE x18,18*REGBYTES(x2)
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STORE x19,19*REGBYTES(x2)
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STORE x20,20*REGBYTES(x2)
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STORE x21,21*REGBYTES(x2)
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STORE x22,22*REGBYTES(x2)
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STORE x23,23*REGBYTES(x2)
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STORE x24,24*REGBYTES(x2)
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STORE x25,25*REGBYTES(x2)
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STORE x26,26*REGBYTES(x2)
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STORE x27,27*REGBYTES(x2)
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STORE x28,28*REGBYTES(x2)
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STORE x29,29*REGBYTES(x2)
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STORE x30,30*REGBYTES(x2)
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STORE x31,31*REGBYTES(x2)
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# save general purpose registers
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# no point in saving x0 since it is always 0
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STORE x1, 1 * REGBYTES(sp)
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# x2 is our stack pointer and is saved further below
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STORE x3, 3 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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# get sr, epc, badvaddr, cause
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csrrw t0,mscratch,x0
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csrr s0,mstatus
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csrr t1,mepc
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csrr t2,mtval
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csrr t3,mcause
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STORE t0,2*REGBYTES(x2)
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STORE s0,32*REGBYTES(x2)
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STORE t1,33*REGBYTES(x2)
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STORE t2,34*REGBYTES(x2)
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STORE t3,35*REGBYTES(x2)
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# get sr, epc, badvaddr, cause
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csrr t0, mscratch
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bnez t0, 1f # t0 == 0, trap come from coreboot
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# t0 != 0, t0 is saved old sp
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add t0, sp, MENTRY_FRAME_SIZE
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1:
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csrr s0, mstatus
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csrr t1, mepc
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csrr t2, mtval
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csrr t3, mcause
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STORE t0, 2 * REGBYTES(sp)
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STORE s0, 32 * REGBYTES(sp)
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STORE t1, 33 * REGBYTES(sp)
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STORE t2, 34 * REGBYTES(sp)
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STORE t3, 35 * REGBYTES(sp)
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# get faulting insn, if it wasn't a fetch-related trap
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li x5,-1
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STORE x5,36*REGBYTES(x2)
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# get faulting insn, if it wasn't a fetch-related trap
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li x5, -1
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STORE x5, 36 * REGBYTES(sp)
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.endm
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.endm
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.globl estack
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.text
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.global trap_entry
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.align 2 # four byte alignment, as required by mtvec
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.text
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.global trap_entry
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.align 2 # four byte alignment, as required by mtvec
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trap_entry:
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csrw mscratch, sp
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# mscratch is initialized to 0
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# when exiting coreboot, write sp to mscratch
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# before jumping to m-mode firmware we always set trap vector to the entry point of the
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# payload and we don't care about mscratch anymore. mscratch is only ever used as
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# exception stack if whatever coreboot jumps to is in s-mode.
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#TODO we could check MPP field in mstatus to see if come from unpriviledged code. That
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# way we could still use mscratch for other purposes inside the code base.
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#TODO In case we got called from s-mode firmware we need to protect our stack and trap
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# handler with a PMP region.
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csrrw sp, mscratch, sp
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# sp == 0 => trap came from coreboot
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# sp != 0 => trap came from s-mode payload
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bnez sp, 1f
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csrrw sp, mscratch, sp
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1:
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addi sp, sp, -MENTRY_FRAME_SIZE
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save_tf
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# SMP isn't supported yet, to avoid overwriting the same stack with different
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# harts that handle traps at the same time.
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# someday this gets fixed.
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//csrr sp, mhartid
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csrr sp, 0xf14
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.Lsmp_hang:
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bnez sp, .Lsmp_hang
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mv a0,sp # put trapframe as first argument
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# Use a different stack than in the main context, to avoid overwriting
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# stack data.
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# TODO: Maybe use the old stack pointer (plus an offset) instead. But only if
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# the previous mode was M, because it would be a very bad idea to use a stack
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# pointer provided by unprivileged code!
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la sp, _estack
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addi sp, sp, -2048 # 2 KiB is half of the stack space
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addi sp, sp, -MENTRY_FRAME_SIZE
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save_tf
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move a0,sp
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# store pointer to stack frame (moved out from trap_handler)
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csrw mscratch, sp
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LOAD t0, trap_handler
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jalr t0
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LOAD t0, trap_handler
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jalr t0
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trap_return:
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csrr a0, mscratch
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restore_regs
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# go back to the previous mode
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addi sp, sp, MENTRY_FRAME_SIZE
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# restore original stack pointer (either sp or mscratch)
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csrrw sp, mscratch, sp
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bnez sp, 1f
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csrrw sp, mscratch, sp
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1:
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mret
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