Drop src/config alltogether
- drop two "newconfig" based files - drop two obsolete doxygen config files and check in our latest Doxyfile.coreboot (that has been used to build coreboot online documentation since 2005 or so) - move two i386 specific linker scripts to src/arch/i386 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
committed by
Stefan Reinauer
Stefan Reinauer
parent
f60a2567d2
commit
531704ed71
@@ -45,9 +45,9 @@ $(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc8
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#######################################################################
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# Build the coreboot_ram (stage 2)
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$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
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$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/i386/coreboot_ram.ld #ldoptions
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
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$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o
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$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
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$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
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100
src/arch/i386/coreboot_apc.ld
Normal file
100
src/arch/i386/coreboot_apc.ld
Normal file
@@ -0,0 +1,100 @@
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/*
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* Memory map:
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*
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* CONFIG_DCACHE_RAM_BASE
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* : data segment
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* : bss segment
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* : heap
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* : stack
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*/
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*/
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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* Rewritten by Eric Biederman
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* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
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* 2006.05 yhlu tailed it to use it for AP code in cache
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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INCLUDE ldoptions
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ENTRY(_start)
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SECTIONS
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{
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. = CONFIG_DCACHE_RAM_BASE;
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text : {
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_text = .;
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*(.text);
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*(.text.*);
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. = ALIGN(16);
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_etext = .;
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}
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.rodata : {
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_rodata = .;
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. = ALIGN(4);
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*(.rodata)
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*(.rodata.*)
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. = ALIGN(4);
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_erodata = .;
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}
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data : {
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_data = .;
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*(.data)
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_edata = .;
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}
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between _bss and _ebss with zeroes.
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*/
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_bss = .;
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.bss . : {
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*(.bss)
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*(.sbss)
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*(COMMON)
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}
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_ebss = .;
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_end = .;
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. = ALIGN(0x1000);
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_stack = .;
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.stack . : {
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. = 0x4000;
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}
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_estack = .;
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_heap = .;
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.heap . : {
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. = ALIGN(4);
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}
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_eheap = .;
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/* The ram segment
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* This is all address of the memory resident copy of coreboot.
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*/
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_ram_seg = _text;
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_eram_seg = _eheap;
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_bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");
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/DISCARD/ : {
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*(.comment)
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*(.note)
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*(.note.*)
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}
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}
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132
src/arch/i386/coreboot_ram.ld
Normal file
132
src/arch/i386/coreboot_ram.ld
Normal file
@@ -0,0 +1,132 @@
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/*
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* Memory map:
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*
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* CONFIG_RAMBASE
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* : data segment
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* : bss segment
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* : heap
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* : stack
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*/
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*/
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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* Rewritten by Eric Biederman
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* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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INCLUDE ldoptions
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ENTRY(_start)
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SECTIONS
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{
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. = CONFIG_RAMBASE;
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text : {
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_text = .;
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*(.text);
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*(.text.*);
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. = ALIGN(16);
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_etext = .;
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}
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.rodata : {
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_rodata = .;
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. = ALIGN(4);
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console_drivers = .;
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*(.rodata.console_drivers)
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econsole_drivers = . ;
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. = ALIGN(4);
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pci_drivers = . ;
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*(.rodata.pci_driver)
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epci_drivers = . ;
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cpu_drivers = . ;
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*(.rodata.cpu_driver)
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ecpu_drivers = . ;
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*(.rodata)
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*(.rodata.*)
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/*
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* kevinh/Ispiri - Added an align, because the objcopy tool
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* incorrectly converts sections that are not long word aligned.
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* This breaks the coreboot.rom target.
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*/
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. = ALIGN(4);
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_erodata = .;
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}
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data : {
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_data = .;
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*(.data)
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_edata = .;
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}
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.sdata : {
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_SDA_BASE_ = .;
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*(.sdata)
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}
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.sdata2 : {
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_SDA2_BASE_ = .;
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*(.sdata2)
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}
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between _bss and _ebss with zeroes.
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*/
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_bss = .;
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.bss . : {
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*(.bss)
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*(.sbss)
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*(COMMON)
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}
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_ebss = .;
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_end = .;
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. = ALIGN(CONFIG_STACK_SIZE);
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_stack = .;
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.stack . : {
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/* Reserve a stack for each possible cpu */
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/* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
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. = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
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}
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_estack = .;
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_heap = .;
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.heap . : {
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/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
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. = CONFIG_HEAP_SIZE ;
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. = ALIGN(4);
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}
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_eheap = .;
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/* The ram segment
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* This is all address of the memory resident copy of coreboot.
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*/
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_ram_seg = _text;
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_eram_seg = _eheap;
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_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP");
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_bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M");
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/DISCARD/ : {
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*(.comment)
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*(.note)
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*(.note.*)
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}
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}
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