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src/mainboard/getac - kontron: Add space around operators

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Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2016-09-19 09:46:33 -06:00
committed by Patrick Georgi
parent 04f8fd981f
commit 531b87ac4e
59 changed files with 476 additions and 476 deletions
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40
src/mainboard/getac/p470/irq_tables.c
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@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x27b0, /* Device */ 0x27b0, /* Device */
@ -29,25 +29,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */ 0xf, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
} }
}; };

4
src/mainboard/getac/p470/romstage.c
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@ -82,7 +82,7 @@ static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT lpt_en = 1 << 2; // enable LPT
} }
// Enable Serial IRQ // Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
@ -126,7 +126,7 @@ static void early_superio_config(void)
{ {
device_t dev; device_t dev;
dev=PNP_DEV(0x4e, 0x00); dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev); pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x02, 0x0e); // UART power pnp_write_register(dev, 0x02, 0x0e); // UART power

14
src/mainboard/gigabyte/ga-6bxc/irq_tables.c
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@ -29,13 +29,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x8, /* Checksum */ 0x8, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
{0x00,(0x07<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x07 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
} }
}; };

8
src/mainboard/gigabyte/ga_2761gxdk/mptable.c
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@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0, sbdn+5, 2, 0x15); // 21 PCI_INT(0, sbdn+5, 2, 0x15); // 21
PCI_INT(0, sbdn+8, 0, 0x16); // 22 PCI_INT(0, sbdn+8, 0, 0x16); // 22
for(j=7; j>=2; j--) { for(j = 7; j >= 2; j--) {
if(!bus_sis966[j]) continue; if(!bus_sis966[j]) continue;
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
} }
} }
for(j=0; j<2; j++) for(j = 0; j < 2; j++)
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
} }

8
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
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@ -89,11 +89,11 @@ static void sio_setup(void)
pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0); dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
} }
@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
enable_fid_change(); enable_fid_change();
@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
#endif #endif

2
src/mainboard/gigabyte/m57sli/fanctl.c
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@ -75,7 +75,7 @@ static const struct {
void init_ec(uint16_t base) void init_ec(uint16_t base)
{ {
int i; int i;
for (i=0; i<ARRAY_SIZE(sequence); i++) { for (i = 0; i < ARRAY_SIZE(sequence); i++) {
write_index(base, sequence[i].index, sequence[i].value); write_index(base, sequence[i].index, sequence[i].value);
} }
} }

14
src/mainboard/gigabyte/m57sli/mptable.c
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@ -84,9 +84,9 @@ static void *smp_write_config_table(void *v)
/* The PCIe slots, each on its own bus */ /* The PCIe slots, each on its own bus */
k = 1; k = 1;
for(i=0; i<4; i++){ for(i = 0; i < 4; i++){
for(j=7; j>1; j--){ for(j = 7; j > 1; j--){
if(k>3) k=0; if(k > 3) k = 0;
PCI_INT(j,0,i, 16+k); PCI_INT(j,0,i, 16+k);
k++; k++;
} }
@ -97,10 +97,10 @@ static void *smp_write_config_table(void *v)
physical PCI slots are j = 7,8 physical PCI slots are j = 7,8
FireWire is j = 10 FireWire is j = 10
*/ */
k=2; k = 2;
for(i=0; i<4; i++){ for(i = 0; i < 4; i++){
for(j=6; j<11; j++){ for(j = 6; j < 11; j++){
if(k>3) k=0; if(k > 3) k = 0;
PCI_INT(1,j,i, 16+k); PCI_INT(1,j,i, 16+k);
k++; k++;
} }

8
src/mainboard/gigabyte/m57sli/romstage.c
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@ -80,11 +80,11 @@ static void sio_setup(void)
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0); dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
} }
@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
enable_fid_change(); enable_fid_change();
@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
#endif #endif

2
src/mainboard/gigabyte/ma785gm/mptable.c
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@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/gigabyte/ma785gm/romstage.c
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@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/gigabyte/ma785gmt/mptable.c
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@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/gigabyte/ma785gmt/romstage.c
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@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/gigabyte/ma78gm/mptable.c
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@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

2
src/mainboard/google/butterfly/chromeos.c
View File

@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
int lidswitch=0; int lidswitch = 0;
if (!gpio_base) if (!gpio_base)
return; return;

2
src/mainboard/google/falco/gma.c
View File

@ -90,7 +90,7 @@ static void palette(void)
unsigned long color = 0; unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){ for(i = 0; i < 256; i++, color += 0x010101){
gtt_write(_LGC_PALETTE_A + (i<<2),color); gtt_write(_LGC_PALETTE_A + (i << 2),color);
} }
} }

4
src/mainboard/google/falco/i915io.c
View File

@ -84,8 +84,8 @@ void runio(struct intel_dp *dp)
gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a); gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a);
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a); gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a);
intel_dp_set_bw(dp); intel_dp_set_bw(dp);
intel_dp_set_lane_count(dp); intel_dp_set_lane_count(dp);

26
src/mainboard/google/link/i915.c
View File

@ -148,7 +148,7 @@ static void palette(void)
unsigned long color = 0; unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){ for(i = 0; i < 256; i++, color += 0x010101){
io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2));
} }
} }
@ -277,57 +277,57 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
index = run(0); index = run(0);
printk(BIOS_SPEW, "Run returns %d\n", index); printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe; auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14);
auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0; auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index); index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index); printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0; auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index); index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index); printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0;
auxout[1] = 0x01000000; auxout[1] = 0x01000000;
/* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
auxout[1] = 0x0a840000; auxout[1] = 0x0a840000;
/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
auxout[2] = 0x00000000; auxout[2] = 0x00000000;
auxout[3] = 0x01000000; auxout[3] = 0x01000000;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x21000000; auxout[1] = 0x21000000;
/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
auxout[1] = 0x00000000; auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x22000000; auxout[1] = 0x22000000;
/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
auxout[1] = 0x00000000; auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index); index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x00000000; auxout[1] = 0x00000000;
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/

2
src/mainboard/google/link/i915io.h
View File

@ -18,7 +18,7 @@
/* things that are, strangely, not defined anywhere? */ /* things that are, strangely, not defined anywhere? */
#define PCH_PP_UNLOCK 0xabcd0000 #define PCH_PP_UNLOCK 0xabcd0000
#define WMx_LP_SR_EN (1<<31) #define WMx_LP_SR_EN (1 << 31)
/* Google Link-specific defines */ /* Google Link-specific defines */
/* how many 4096-byte pages do we need for the framebuffer? /* how many 4096-byte pages do we need for the framebuffer?

2
src/mainboard/google/peppy/gma.c
View File

@ -91,7 +91,7 @@ static void palette(void)
unsigned long color = 0; unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){ for(i = 0; i < 256; i++, color += 0x010101){
gtt_write(_LGC_PALETTE_A + (i<<2),color); gtt_write(_LGC_PALETTE_A + (i << 2),color);
} }
} }

4
src/mainboard/hp/dl145_g1/acpi_tables.c
View File

@ -25,7 +25,7 @@
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned int gsi_base=0x18; unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i; int i;
int j = 0; int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0; unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4 // 8131 need to use +4

12
src/mainboard/hp/dl145_g1/fadt.c
View File

@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->oem_table_id,"COREBOOT",8);
memcpy(header->asl_compiler_id,ASLC,4); memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0; header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt; fadt->dsdt= (u32)dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
fadt->preferred_pm_profile=0x04; fadt->preferred_pm_profile = 0x04;
fadt->sci_int=9; fadt->sci_int = 9;
// disable system management mode by setting to 0: // disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f; fadt->smi_cmd = 0;//pm_base+0x2f;
@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->cst_cnt = 0xe3; fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
fadt->flush_size = 0; // ignored if wbindv=1 in flags fadt->flush_size = 0; // ignored if wbindv = 1 in flags
fadt->flush_stride = 0; // ignored if wbindv=1 in flags fadt->flush_stride = 0; // ignored if wbindv = 1 in flags
fadt->duty_offset = 1; fadt->duty_offset = 1;
fadt->duty_width = 3; // 0 means duty cycle not supported fadt->duty_width = 3; // 0 means duty cycle not supported
// _alrm value 0 means RTC alarm feature not supported // _alrm value 0 means RTC alarm feature not supported

4
src/mainboard/hp/dl145_g1/get_bus_conf.c
View File

@ -52,7 +52,7 @@ void get_bus_conf(void)
device_t dev; device_t dev;
int i; int i;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
@ -60,7 +60,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m = sysconf.mb; struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }

2
src/mainboard/hp/dl145_g1/irq_tables.c
View File

@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++; pirq_info++;
slot_num++; slot_num++;
//pcix bridge //pcix bridge
// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++; // pirq_info++; slot_num++;
pirq_info++; pirq_info++;

30
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -28,12 +28,12 @@ static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
/* Set the memreset low. */ /* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */ /* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} else { } else {
/* Ensure the CPU has control of the memory lines. */ /* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} }
} }
@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
udelay(800); udelay(800);
/* Set memreset high. */ /* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90); udelay(90);
} }
} }
@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
{ {
int ret,i; int ret,i;
unsigned device=(ctrl->channel0[0])>>8; unsigned device=(ctrl->channel0[0])>>8;
/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
i=2; i = 2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret!=0) && (i-->0)); } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0); smbus_write_byte(SMBUS_HUB, 0x03, 0);
} }
@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device)
{ {
int ret, i; int ret, i;
printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device); printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
i=2; i = 2;
do { do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device); ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret); printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
} while ((ret!=0) && (i-->0)); } while ((ret != 0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
} }
@ -91,8 +91,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c" #include "cpu/amd/model_fxx/fidvid.c"
#endif #endif
#define RC0 ((1<<1)<<8) #define RC0 ((1 << 1)<<8)
#define RC1 ((1<<2)<<8) #define RC1 ((1 << 2)<<8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus(); enable_smbus();
int i; int i;
for(i=0;i<2;i++) { for(i = 0; i < 2; i++) {
activate_spd_rom(&sysinfo->ctrl[i]); activate_spd_rom(&sysinfo->ctrl[i]);
} }
for(i=RC0;i<=RC1;i<<=1) { for(i = RC0; i <= RC1; i<<=1) {
change_i2c_mux(i); change_i2c_mux(i);
} }

6
src/mainboard/hp/dl145_g3/get_bus_conf.c
View File

@ -68,7 +68,7 @@ void get_bus_conf(void)
int i; int i;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
@ -78,7 +78,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
@ -125,6 +125,6 @@ void get_bus_conf(void)
apicid_base = get_apicid_base(3); apicid_base = get_apicid_base(3);
else else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
for(i=0;i<3;i++) for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i; m->apicid_bcm5785[i] = apicid_base+i;
} }

74
src/mainboard/hp/dl145_g3/irq_tables.c
View File

@ -5,45 +5,45 @@
#endif #endif
static const struct irq_routing_table intel_irq_routing_table = { static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x0, /* Where the interrupt router lies (bus) */ 0x0, /* Where the interrupt router lies (bus) */
(0x2<<3)|0x4, (0x2 << 3)|0x4,
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0, /* Vendor */ 0, /* Vendor */
0, /* Device */ 0, /* Device */
0, /* Miniport data */ 0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x2a, /* u8 checksum. This has to be set to some 0x2a, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all value that would give 0 after the sum of all
bytes for this structure (including checksum) */ bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
{0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
{0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
{0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
{0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
{0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
{0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
//{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
{0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
//{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
{0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
{0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
{0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
//{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
//{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
{0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
{0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
//{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
{0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
} }
}; };
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
return copy_pirq_routing_table(addr, &intel_irq_routing_table); return copy_pirq_routing_table(addr, &intel_irq_routing_table);
} }

38
src/mainboard/hp/dl145_g3/mptable.c
View File

@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com> * Copyright (C) 2001 Eric W.Biederman <ebiderman@lnxi.com>
* *
* Copyright (C) 2006 AMD * Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu@gmail.com> for AMD. * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0; device_t dev = 0;
int i; int i;
struct resource *res; struct resource *res;
for(i=0; i<3; i++) { for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev); dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
if(dev) { if(dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x64); dword = pci_read_config32(dev, 0x64);
dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword); pci_write_config32(dev, 0x64, dword);
} }
// set GEVENT pins to NO OP // set GEVENT pins to NO OP
@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x64); dword = pci_read_config32(dev, 0x64);
dword |= (1<<26); dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword); pci_write_config32(dev, 0x64, dword);
} }
} }
@ -116,32 +116,32 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0); mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//SATA //SATA
/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ /* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */ /* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
//USB //USB
printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa);
//VGA //VGA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7);
//PCIE //PCIE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe);
//IDE //IDE
// outb(0x02, 0xc00); outb(0x0e, 0xc01); // outb(0x02, 0xc00); outb(0x0e, 0xc01);
// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe);
//onboard Broadcom GbE //onboard Broadcom GbE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4);
@ -153,7 +153,7 @@ static void *smp_write_config_table(void *v)
if(dev) { if(dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x6c); dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword); printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword); pci_write_config32(dev, 0x6c, dword);
} }

22
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -79,11 +79,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void setup_early_ipmi_serial() static void setup_early_ipmi_serial()
{ {
unsigned char result; unsigned char result;
char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05}; char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05};
char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f}; char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f};
char serial_mux1[]={0x0c<<2,0x12,0x04,0x06}; char serial_mux1[]={0x0c << 2,0x12,0x04,0x06};
char serial_mux2[]={0x0c<<2,0x12,0x04,0x03}; char serial_mux2[]={0x0c << 2,0x12,0x04,0x03};
char serial_mux3[]={0x0c<<2,0x12,0x04,0x07}; char serial_mux3[]={0x0c << 2,0x12,0x04,0x07};
// earlydbg(0x0d); // earlydbg(0x0d);
//set channel access system only //set channel access system only
@ -91,19 +91,19 @@ static void setup_early_ipmi_serial()
// earlydbg(result); // earlydbg(result);
/* /*
//Set serial/modem config //Set serial/modem config
result=ipmi_request(6,serialmodem_conf); result = ipmi_request(6,serialmodem_conf);
earlydbg(result); earlydbg(result);
//Set serial mux 1 //Set serial mux 1
result=ipmi_request(4,serial_mux1); result = ipmi_request(4,serial_mux1);
earlydbg(result); earlydbg(result);
//Set serial mux 2 //Set serial mux 2
result=ipmi_request(4,serial_mux2); result = ipmi_request(4,serial_mux2);
earlydbg(result); earlydbg(result);
//Set serial mux 3 //Set serial mux 3
result=ipmi_request(4,serial_mux3); result = ipmi_request(4,serial_mux3);
earlydbg(result); earlydbg(result);
*/ */
// earlydbg(0x0e); // earlydbg(0x0e);
@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
} }
enable_fid_change(); enable_fid_change();
@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
} }
#endif #endif

6
src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
View File

@ -69,7 +69,7 @@ void get_bus_conf(void)
int i; int i;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
@ -80,7 +80,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
@ -124,6 +124,6 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
apicid_base = 0x10; apicid_base = 0x10;
for(i=0;i<3;i++) for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i; m->apicid_bcm5785[i] = apicid_base+i;
} }

30
src/mainboard/hp/dl165_g6_fam10/mptable.c
View File

@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com> * Copyright (C) 2001 Eric W.Biederman < ebiderman@lnxi.com>
* *
* Copyright (C) 2006 AMD * Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu@gmail.com> for AMD. * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0; device_t dev = 0;
int i; int i;
struct resource *res; struct resource *res;
for(i=0; i<3; i++) { for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev); dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
if(dev) { if(dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x64); dword = pci_read_config32(dev, 0x64);
dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword); pci_write_config32(dev, 0x64, dword);
} }
// set GEVENT pins to NO OP // set GEVENT pins to NO OP
@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
if (dev) { if (dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x64); dword = pci_read_config32(dev, 0x64);
dword |= (1<<26); dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword); pci_write_config32(dev, 0x64, dword);
} }
} }
@ -113,16 +113,16 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
/* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0, m->apicid_bcm5785[0], 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0, m->apicid_bcm5785[0], 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0, m->apicid_bcm5785[2], 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1, m->apicid_bcm5785[2], 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0, m->apicid_bcm5785[2], 0xa);
/* enable int */ /* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
if(dev) { if(dev) {
uint32_t dword; uint32_t dword;
dword = pci_read_config32(dev, 0x6c); dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword); printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword); pci_write_config32(dev, 0x6c, dword);
} }

2
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

40
src/mainboard/ibase/mb899/irq_tables.c
View File

@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x27b9, /* Device */ 0x27b9, /* Device */
@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */ 0xf, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053 {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
} }
}; };

16
src/mainboard/ibase/mb899/romstage.c
View File

@ -87,14 +87,14 @@ static void early_superio_config_w83627ehg(void)
pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
dev=PNP_DEV(0x4e, W83627EHG_SP1); dev = PNP_DEV(0x4e, W83627EHG_SP1);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_SP2); dev = PNP_DEV(0x4e, W83627EHG_SP2);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
@ -102,7 +102,7 @@ static void early_superio_config_w83627ehg(void)
// pnp_write_config(dev, 0xf1, 4); // IRMODE0 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@ -110,27 +110,27 @@ static void early_superio_config_w83627ehg(void)
//pnp_write_config(dev, 0xf0, 0x82); //pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_GPIO2); dev = PNP_DEV(0x4e, W83627EHG_GPIO2);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it pnp_set_enable(dev, 1); // Just enable it
dev=PNP_DEV(0x4e, W83627EHG_GPIO3); dev = PNP_DEV(0x4e, W83627EHG_GPIO3);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
dev=PNP_DEV(0x4e, W83627EHG_FDC); dev = PNP_DEV(0x4e, W83627EHG_FDC);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627EHG_PP); dev = PNP_DEV(0x4e, W83627EHG_PP);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
/* Enable HWM */ /* Enable HWM */
dev=PNP_DEV(0x4e, W83627EHG_HWM); dev = PNP_DEV(0x4e, W83627EHG_HWM);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);

2
src/mainboard/iei/kino-780am2-fam10/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

18
src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
View File

@ -57,7 +57,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[0] = { [0] = {
.slot = 0x0, /* means also "on board" */ .slot = 0x0, /* means also "on board" */
.bus = 0x00, .bus = 0x00,
.devfn = (0x01<<3)|0x0, /* 0x01 is CS5536 */ .devfn = (0x01 << 3)|0x0, /* 0x01 is CS5536 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA, .link = LINK_PIRQA,
@ -81,7 +81,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[1] = { [1] = {
.slot = 0x0, /* means also "on board" */ .slot = 0x0, /* means also "on board" */
.bus = 0x00, .bus = 0x00,
.devfn = (0x0f<<3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */ .devfn = (0x0f << 3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_NONE, .link = LINK_NONE,
@ -105,7 +105,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[2] = { [2] = {
.slot = 0x0, /* means also "on board" */ .slot = 0x0, /* means also "on board" */
.bus = 0x00, .bus = 0x00,
.devfn = (0x0e<<3)|0x0, /* 0x0e is eth0 */ .devfn = (0x0e << 3)|0x0, /* 0x0e is eth0 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD, .link = LINK_PIRQD,
@ -129,7 +129,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[3] = { [3] = {
.slot = 0x0, /* means also "on board" */ .slot = 0x0, /* means also "on board" */
.bus = 0x00, .bus = 0x00,
.devfn = (0x10<<3)|0x0, /* 0x10 is eth1 */ .devfn = (0x10 << 3)|0x0, /* 0x10 is eth1 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB, .link = LINK_PIRQB,
@ -153,7 +153,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[4] = { [4] = {
.slot = 0x0, /* means also "on board" */ .slot = 0x0, /* means also "on board" */
.bus = 0x00, .bus = 0x00,
.devfn = (0x11<<3)|0x0, /* 0x11 is SATA */ .devfn = (0x11 << 3)|0x0, /* 0x11 is SATA */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA, .link = LINK_PIRQA,
@ -184,7 +184,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[5] = { [5] = {
.slot = 0x1, /* This is real PCI slot. */ .slot = 0x1, /* This is real PCI slot. */
.bus = 0x00, .bus = 0x00,
.devfn = (0x09<<3)|0x0, /* 0x09 is PCI1 */ .devfn = (0x09 << 3)|0x0, /* 0x09 is PCI1 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA, .link = LINK_PIRQA,
@ -210,7 +210,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[6] = { [6] = {
.slot = 0x2, /* This is real PCI slot. */ .slot = 0x2, /* This is real PCI slot. */
.bus = 0x00, .bus = 0x00,
.devfn = (0x0a<<3)|0x0, /* 0x0a is PCI2 */ .devfn = (0x0a << 3)|0x0, /* 0x0a is PCI2 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD, .link = LINK_PIRQD,
@ -236,7 +236,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[7] = { [7] = {
.slot = 0x3, /* This is real PCI slot. */ .slot = 0x3, /* This is real PCI slot. */
.bus = 0x00, .bus = 0x00,
.devfn = (0x0b<<3)|0x0, /* 0x0b is PCI3 */ .devfn = (0x0b << 3)|0x0, /* 0x0b is PCI3 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQC, .link = LINK_PIRQC,
@ -262,7 +262,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[8] = { [8] = {
.slot = 0x4, /* This is real PCI slot. */ .slot = 0x4, /* This is real PCI slot. */
.bus = 0x00, .bus = 0x00,
.devfn = (0x0c<<3)|0x0, /* 0x0c is PCI4 */ .devfn = (0x0c << 3)|0x0, /* 0x0c is PCI4 */
.irq = { .irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */ [0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB, .link = LINK_PIRQB,

40
src/mainboard/intel/d945gclf/irq_tables.c
View File

@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*18, /* There can be total 18 devices on the bus */ 32+16*18, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x27b0, /* Device */ 0x27b0, /* Device */
@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */ 0xf, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
} }
}; };

6
src/mainboard/intel/eagleheights/debug.c
View File

@ -61,13 +61,13 @@ static inline void siodump(void)
unsigned char data; unsigned char data;
printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n"); printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) { for (i = 0x10; i <= 0x2d; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
#if 0 #if 0
printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");
setup_func(0x0f); setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) { for (i = 0xf0; i <= 0xff; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
@ -82,7 +82,7 @@ static inline void siodump(void)
#endif #endif
printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n");
setup_func(0x07); setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) { for (i = 0xf0; i <= 0xf8; i++) {
print_reg((unsigned char)i); print_reg((unsigned char)i);
} }
printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n");

28
src/mainboard/intel/littleplains/irq_tables.c
View File

@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x0F1C, /* Device */ 0x0F1C, /* Device */
@ -41,19 +41,19 @@ const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x86, /* u8 checksum. */ 0x86, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
{0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
{0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
{0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
{0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
{0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
{0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
} }
}; };

28
src/mainboard/intel/mohonpeak/irq_tables.c
View File

@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x0F1C, /* Device */ 0x0F1C, /* Device */
@ -41,19 +41,19 @@ const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x86, /* u8 checksum. */ 0x86, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
{0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
{0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
{0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
{0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
{0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
{0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
{0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
{0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
} }
}; };

26
src/mainboard/intel/mtarvon/mptable.c
View File

@ -47,31 +47,31 @@ static void *smp_write_config_table(void *v)
/* Internal PCI devices */ /* Internal PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */ 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */ 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */ 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */ 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */ 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */ 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */ 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */ 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */ 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */ 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */ 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */ 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|3, 0x01, 0x13); /* ? */ 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */
/* PCI slot */ /* PCI slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,

34
src/mainboard/intel/truxton/mptable.c
View File

@ -75,50 +75,50 @@ static void *smp_write_config_table(void *v)
/* IMCH/IICH PCI devices */ /* IMCH/IICH PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */ 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */ 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */ 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */ 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */ 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */
if (bus_pea0) { if (bus_pea0) {
/* PCIe slot 0 */ /* PCIe slot 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|0, 0x8, 0x10); bus_pea0, (0 << 2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|1, 0x8, 0x11); bus_pea0, (0 << 2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|2, 0x8, 0x12); bus_pea0, (0 << 2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|3, 0x8, 0x13); bus_pea0, (0 << 2)|3, 0x8, 0x13);
} }
if (bus_pea1) { if (bus_pea1) {
/* PCIe slots 1-4 */ /* PCIe slots 1-4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|0, 0x8, 0x10); bus_pea1, (0 << 2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|1, 0x8, 0x11); bus_pea1, (0 << 2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|2, 0x8, 0x12); bus_pea1, (0 << 2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|3, 0x8, 0x13); bus_pea1, (0 << 2)|3, 0x8, 0x13);
} }
if (bus_aioc) { if (bus_aioc) {
/* AIOC PCI devices */ /* AIOC PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */ bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */ bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */ bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */
} }
/* There is no extension information... */ /* There is no extension information... */

2
src/mainboard/intel/wtm2/graphics.c
View File

@ -23,7 +23,7 @@ void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
io_i915_write32(0x80000000,0x45400); io_i915_write32(0x80000000,0x45400);
io_i915_write32(0x00000000,_CURACNTR); io_i915_write32(0x00000000,_CURACNTR);
io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR); io_i915_write32((/* PIPEA */0x0 << 24)|0x00000000,_DSPACNTR);
io_i915_write32(0x00000000,_DSPBCNTR); io_i915_write32(0x00000000,_DSPBCNTR);
io_i915_write32(0x80000000,CPU_VGACNTRL); io_i915_write32(0x80000000,CPU_VGACNTRL);
io_i915_write32(0x00000000,_DSPASIZE+0xc); io_i915_write32(0x00000000,_DSPASIZE+0xc);

2
src/mainboard/iwave/iWRainbowG6/romstage.c
View File

@ -219,7 +219,7 @@ void transaction3(unsigned char dev_addr)
// sch_SMbus_regs (); // sch_SMbus_regs ();
//check the status register for busy state //check the status register for busy state
//temp=inb(SMBusBase+SMBHSTSTS); //temp = inb(SMBusBase+SMBHSTSTS);
//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp); //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
//sch_SMbus_regs (); //sch_SMbus_regs ();
//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS)); //printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));

8
src/mainboard/iwill/dk8_htx/acpi_tables.c
View File

@ -24,7 +24,7 @@
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)
{ {
unsigned int gsi_base=0x18; unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i; int i;
int j = 0; int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0; unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4 // 8131 need to use +4
@ -144,11 +144,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
const char *file_name; const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue; if((sysconf.pci1234[i] & 1) != 1 ) continue;
uint8_t c; uint8_t c;
if(i<7) { if(i < 7) {
c = (uint8_t) ('4' + i - 1); c = (uint8_t) ('4' + i - 1);
} }
else { else {

8
src/mainboard/iwill/dk8_htx/fadt.c
View File

@ -23,13 +23,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id,ASLC,4); memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0; header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs; fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt; fadt->dsdt= (u32)dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server // 3=Workstation, 4=Enterprise Server, 7=Performance Server
fadt->preferred_pm_profile=0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int=9; fadt->sci_int = 9;
// disable system management mode by setting to 0: // disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f; fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0; fadt->acpi_enable = 0xf0;

2
src/mainboard/iwill/dk8_htx/irq_tables.c
View File

@ -111,7 +111,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num++; slot_num++;
//pcix bridge //pcix bridge
// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++; // pirq_info++; slot_num++;
int j = 0; int j = 0;

186
src/mainboard/iwill/dk8_htx/mptable.c
View File

@ -12,15 +12,15 @@
static void *smp_write_config_table(void *v) static void *smp_write_config_table(void *v)
{ {
struct mp_config_table *mc; struct mp_config_table *mc;
int i, j, bus_isa; int i, j, bus_isa;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR); mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
@ -30,143 +30,143 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111 smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
res2mmio(res, 0, 0)); res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
res2mmio(res, 0, 0)); res2mmio(res, 0, 0));
} }
} }
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) { switch(sysconf.hcid[i]) {
case 1: // 8132 case 1: // 8132
case 3: // 8131 case 3: // 8131
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11,
res2mmio(res, 0, 0)); res2mmio(res, 0, 0));
} }
} }
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11,
res2mmio(res, 0, 0)); res2mmio(res, 0, 0));
} }
} }
break; break;
} }
j++; j++;
} }
} }
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
//??? What //??? What
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB // Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
// Onboard VGA // Onboard VGA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12);
//Slot 5 PCI 32 //Slot 5 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
} }
//Slot 6 PCI 32 //Slot 6 PCI 32
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
} }
//Slot 1: HTX //Slot 1: HTX
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30
} }
//Slot 3 PCI-X 133/100/66 //Slot 3 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
} }
//Slot 4 PCI-X 133/100/66 //Slot 4 PCI-X 133/100/66
for(i=0;i<4;i++) { for(i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26
} }
//Onboard NICS //Onboard NICS
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24
//Onboard SATA //Onboard SATA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25
j = 0; j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii; int ii;
device_t dev; device_t dev;
struct resource *res; struct resource *res;
switch(sysconf.hcid[i]) { switch(sysconf.hcid[i]) {
case 1: case 1:
case 3: case 3:
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
//Slot 1 PCI-X 133/100/66 //Slot 1 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
} }
} }
} }
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
//Slot 2 PCI-X 133/100/66 //Slot 2 PCI-X 133/100/66
for(ii=0;ii<4;ii++) { for(ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
} }
} }
} }
break; break;
case 2: case 2:
// Slot AGP // Slot AGP
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
break; break;
} }
j++; j++;
} }

12
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -28,12 +28,12 @@ static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
/* Set the memreset low. */ /* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */ /* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} else { } else {
/* Ensure the CPU has control of the memory lines. */ /* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} }
} }
@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
udelay(800); udelay(800);
/* Set memreset_high */ /* Set memreset_high */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90); udelay(90);
} }
} }
@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID #if CONFIG_SET_FIDVID
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
enable_fid_change(); enable_fid_change();
@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
} }
#endif #endif

22
src/mainboard/jetway/j7f2/irq_tables.c
View File

@ -30,17 +30,17 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */ 0x3e, /* Checksum */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
{0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
{0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
{0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
{0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
} }
}; };

4
src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
View File

@ -66,10 +66,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
/* Get SB800 MMIO Base (AcpiMmioAddr) */ /* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27); WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16=Data8<<8; Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26); WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7); Data8 = ReadIo8(0xCD7);
Data16|=Data8; Data16 |= Data8;
AcpiMmioAddr = (uint32_t)Data16 << 16; AcpiMmioAddr = (uint32_t)Data16 << 16;
Status = AGESA_UNSUPPORTED; Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

2
src/mainboard/jetway/pa78vm5/mptable.c
View File

@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

2
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A); post_code(0x3A);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010071); msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif #endif

40
src/mainboard/kontron/986lcd-m/irq_tables.c
View File

@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */ 0x8086, /* Vendor */
0x27b0, /* Device */ 0x27b0, /* Device */
@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */ 0xf, /* u8 checksum. */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
} }
}; };

32
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -57,7 +57,7 @@ static void ich7_enable_lpc(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) { if (read_option(lpt, 0) != 0) {
lpt_en = 1<<2; // enable LPT lpt_en = 1 << 2; // enable LPT
} }
// Enable Serial IRQ // Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
@ -98,7 +98,7 @@ static void early_superio_config_w83627thg(void)
{ {
device_t dev; device_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1); dev = PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_func_mode(dev); pnp_enter_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc6); // PNPCSV pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
@ -106,14 +106,14 @@ static void early_superio_config_w83627thg(void)
pnp_write_config(dev, 0x29, 0x43); // GPIO settings pnp_write_config(dev, 0x29, 0x43); // GPIO settings
pnp_write_config(dev, 0x2a, 0x40); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
dev=PNP_DEV(0x2e, W83627THG_SP1); dev = PNP_DEV(0x2e, W83627THG_SP1);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x2e, W83627THG_SP2); dev = PNP_DEV(0x2e, W83627THG_SP2);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
@ -121,7 +121,7 @@ static void early_superio_config_w83627thg(void)
// pnp_write_config(dev, 0xf1, 4); // IRMODE0 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x2e, W83627THG_KBC); dev = PNP_DEV(0x2e, W83627THG_KBC);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@ -129,33 +129,33 @@ static void early_superio_config_w83627thg(void)
// pnp_write_config(dev, 0xf0, 0x82); // pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x2e, W83627THG_GPIO2); dev = PNP_DEV(0x2e, W83627THG_GPIO2);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it pnp_set_enable(dev, 1); // Just enable it
dev=PNP_DEV(0x2e, W83627THG_GPIO3); dev = PNP_DEV(0x2e, W83627THG_GPIO3);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
dev=PNP_DEV(0x2e, W83627THG_FDC); dev = PNP_DEV(0x2e, W83627THG_FDC);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
dev=PNP_DEV(0x2e, W83627THG_PP); dev = PNP_DEV(0x2e, W83627THG_PP);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
/* Enable HWM */ /* Enable HWM */
dev=PNP_DEV(0x2e, W83627THG_HWM); dev = PNP_DEV(0x2e, W83627THG_HWM);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
@ -163,7 +163,7 @@ static void early_superio_config_w83627thg(void)
pnp_exit_func_mode(dev); pnp_exit_func_mode(dev);
dev=PNP_DEV(0x4e, W83627THG_SP1); dev = PNP_DEV(0x4e, W83627THG_SP1);
pnp_enter_func_mode(dev); pnp_enter_func_mode(dev);
pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
@ -172,22 +172,22 @@ static void early_superio_config_w83627thg(void)
pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627THG_SP2); dev = PNP_DEV(0x4e, W83627THG_SP2);
pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 10); pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627THG_FDC); dev = PNP_DEV(0x4e, W83627THG_FDC);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627THG_PP); dev = PNP_DEV(0x4e, W83627THG_PP);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627THG_KBC); dev = PNP_DEV(0x4e, W83627THG_KBC);
pnp_set_logical_device(dev); pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);

6
src/mainboard/kontron/kt690/fadt.c
View File

@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs; fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt; fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */ /* 3=Workstation, 4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03; fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9; fadt->sci_int = 9;
/* disable system management mode by setting to 0: */ /* disable system management mode by setting to 0: */
@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at * the contents of the PM registers at
* index 20-2B to decode ACPI I/O address. * index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/ * AcpiSmiEn & SmiCmdEn*/
pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;

2
src/mainboard/kontron/kt690/mptable.c
View File

@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac); dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26); dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword); pci_write_config32(dev, 0xac, dword);
/* /*

4
src/mainboard/kontron/kt690/romstage.c
View File

@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007); cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) { if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */ /* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change(); enable_fid_change();
@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */ /* show final fid and vid */
msr=rdmsr(0xc0010042); msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else { } else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_DEBUG, "Changing FIDVID not supported\n");