diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md new file mode 100644 index 0000000000..326756199b --- /dev/null +++ b/Documentation/mainboard/clevo/n130wu/index.md @@ -0,0 +1,47 @@ +# Clevo N130WU + +## Hardware +### Technology +```eval_rst ++------------------+--------------------------------+ +| CPU | Intel i7-8550U | ++------------------+--------------------------------+ +| PCH | Intel Sunrise Point LP | ++------------------+--------------------------------+ +| EC / Super IO | ITE IT8587E | ++------------------+--------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------+ +``` + +### Flash chip +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Model | GD25Q64B | ++---------------------+-----------------+ +| Socketed flash | no | ++---------------------+-----------------+ +| Size | 8 MiB | ++---------------------+-----------------+ +| In circuit flashing | Yes | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Write protection | No | ++---------------------+-----------------+ +| Dual BIOS feature | No | ++---------------------+-----------------+ +| Internal flashing | Yes | ++---------------------+-----------------+ +``` + +## Board status +### Working +### Not Working +### Work in progress +### Untested + +## Also known as +* TUXEDO InfinityBook Pro 13 v3 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4a1f74bc42..d6aed22128 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,6 +26,10 @@ This section contains documentation about coreboot on specific mainboards. - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Clevo + +- [N130WU / N131WU](clevo/n130wu/index.md) + ## Dell - [OptiPlex 9010 SFF](dell/optiplex_9010.md) diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 139fa20865..ae973d401c 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -1,14 +1,89 @@ -Upcoming release - coreboot 4.13 +coreboot 4.13 ================================ -The 4.13 release is planned for November 2020. +coreboot 4.13 was released on November 20th, 2020. -Update this document with changes that should be in the release notes. +Since 4.12 there were 4200 new commits by over 234 developers. +Of these, about 72 contributed to coreboot for the first time. -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +Thank you to all developers who again helped made coreboot better +than ever, and a big welcome to our new contributors! + +New mainboards +-------------- + +- Acer G43T-AM3 +- AMD Cereme +- Asus A88XM-E FM2+ +- Biostar TH61-ITX +- BostenTech GBYT4 +- Clevo L140CU/L141CU +- Dell OptiPlex 9010 +- Example Min86 (fake board) +- Google Ambassador +- Google Asurada +- Google Berknip +- Google Boldar +- Google Boten +- Google Burnet +- Google Cerise +- Google Coachz +- Google Dalboz +- Google Dauntless +- Google Delbin +- Google Dirinboz +- Google Dooly +- Google Drawcia +- Google Eldrid +- Google Elemi +- Google Esche +- Google Ezkinil +- Google Faffy +- Google Fennel +- Google Genesis +- Google Hayato +- Google Lantis +- Google Lindar +- Google Madoo +- Google Magolor +- Google Metaknight +- Google Morphius +- Google Noibat +- Google Pompom +- Google Shuboz +- Google Stern +- Google Terrador +- Google Todor +- Google Trembyle +- Google Vilboz +- Google Voema +- Google Volteer2 +- Google Voxel +- Google Willow +- Google Woomax +- Google Wyvern +- HP EliteBook 2560p +- HP EliteBook Folio 9480m +- HP ProBook 6360b +- Intel Alderlake-P RVP +- Kontron COMe-bSL6 +- Lenovo ThinkPad X230s +- Open Compute Project DeltaLake +- Prodrive Hermes +- Purism Librem Mini +- Purism Librem Mini v2 +- Siemens Chili +- Supermicro X11SSH-F +- System76 lemp9 + +Removed mainboards +------------------ + +- Google Cheza +- Google DragonEgg +- Google Ripto +- Google Sushi +- Open Compute Project SonoraPass Significant changes ------------------- @@ -62,11 +137,11 @@ the platforms. More details about the tools are added in ### New version of SMM loader -A new version of the SMM loader which accomodates platforms with over 32 CPU +A new version of the SMM loader which accommodates platforms with over 32 CPU threads. The existing version of SMM loader uses a 64K code/data segment and only a limited number of CPU threads can fit into one segment (because of save state, STM, other features, etc). This loader extends beyond -the 64K segment to accomodate additional CPUs and in theory allows as many +the 64K segment to accommodate additional CPUs and in theory allows as many CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. @@ -81,11 +156,81 @@ more info. ### Initial support for x86_64 -The x86_64 code support has been revived and enabled for qemu. While it started +The x86_64 code support has been revived and enabled for QEMU. While it started as PoC and the only supported platform is an emulator, there's interest in enabling additional platforms. It would allow to access more than 4GiB of memory at runtime and possibly brings optimised code for faster execution times. It still needs changes in assembly, fixed integer to pointer conversions in C, wrappers for blobs, support for running Option ROMs, among other things. -### Add significant changes here +### Preparations to minimize enabling PCI bus mastering + +For security reasons, bus mastering should be enabled as late as possible. In +coreboot, it's usually not necessary and payloads should only enable it for +devices they use. Since not all payloads enable bus mastering properly yet, +some Kconfig options were added as an intermediate step to give some sort of +"backwards compatibility", which allow enabling or disabling bus mastering by +groups. + +Currently available groups are: + +* PCI bridges +* Any devices + +For now, "Any devices" is enabled by default to keep the traditional behaviour, +which also includes all other options. This is currently necessary, for instance, +for libpayload-based payloads as the drivers don't enable bus mastering for PCI +bridges. + +Exceptional cases, that may still need early bus master enabling in the future, +should get their own per-reason Kconfig option. Ideally before the next release. + +### Early runtime configurability of the console log level + +Traditionally, we didn't allow the log level of the `romstage` console +to be changed at runtime (e.g. via `get_option()`). It turned out that +the technical constraints for this (no global variables in `romstage`) +vanished long ago, though. The new behaviour is to query `get_option()` +now from the second stage that uses the console on. In other words, if +the `bootblock` already enables the console, the `romstage` log level +can be changed via `get_option()`. Keeping the log level of the first +console static ensures that we can see console output even if there's +a bug in the more involved code to query options. + +### Resource allocator v4 + +A new revision of resource allocator v4 is now added to coreboot that supports +mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does +not use the topmost available window for allocation. Instead, it uses the first +window within the address space that is available and satisfies the resource request. +This allows utilization of the entire available address space and also allows +allocation above the 4G boundary. The old resource allocator v3 is still retained for +some AMD platforms that do not conform to the requirements of the allocator. + +Deprecations +------------ + +### PCI bus master configuration options + +In order to minimize the usage of PCI bus mastering, the options we introduced in +this release will be dropped in a future release again. For more details, please +see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). + +### Resource allocator v3 + +Resource allocator v3 is retained in coreboot tree because the following platforms +do not conform to the requirements of the resource allocation i.e. not all the fixed +resources of the platform are provided during the `read_resources()` operation: + +* northbridge/amd/pi/00630F01 +* northbridge/amd/pi/00730F01 +* northbridge/amd/pi/00660F01 +* northbridge/amd/agesa/family14 +* northbridge/amd/agesa/family15tn +* northbridge/amd/agesa/family16kb + +In order to have a single unified allocator in coreboot, this notice is being added +to ensure that the platforms listed above are fixed before the next release. If there +is interest in maintaining support for these platforms beyond the next release, +please ensure that the platforms are fixed to conform to the expectations of resource +allocation. diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md new file mode 100644 index 0000000000..43a8d0dc0b --- /dev/null +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -0,0 +1,16 @@ +Upcoming release - coreboot 4.14 +================================ + +The 4.14 release is planned for May 2021. + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 0575e93f3b..081d1fc89c 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -13,6 +13,7 @@ Release notes for previous releases * [4.10 - July 2019](coreboot-4.10-relnotes.md) * [4.11 - November 2019](coreboot-4.11-relnotes.md) * [4.12 - May 2020](coreboot-4.12-relnotes.md) +* [4.13 - November 2020](coreboot-4.13-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -24,4 +25,4 @@ Upcoming release ---------------- Please add to the release notes as changes are added: -* [4.13 - November 2020](coreboot-4.13-relnotes.md) +* [4.14 - May 2021](coreboot-4.14-relnotes.md) diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index c0ccfceafb..b94901b55c 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -8,6 +8,8 @@ - Facebook Monolith ## Google +- Asurada +- Hayato - Auron_Paine (Acer C740 Chromebook) - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531)) - Buddy (Acer Chromebase 24) @@ -34,7 +36,6 @@ - Daisy (Samsung Chromebook (2012)) - Deltan - Deltaur -- DragonEgg - Drallion - Eve (Google Pixelbook) - Fizz @@ -57,9 +58,12 @@ - Rainier - Akemi - Dratini +- Duffy Legacy (32MB) - Duffy +- Faffy - Hatch - Jinlon +- Kaisa Legacy (32MB) - Kaisa - Kohaku - Kindred @@ -67,10 +71,14 @@ - Mushu - Palkia - Nightfury +- Noibat - Puff - Helios_Diskswap - Stryke -- Sushi +- Wyvern +- Dooly +- Ambassador +- Genesis - Guado (ASUS Chromebox CN62) - Jecht - Rikku (Acer Chromebox CXI2) @@ -90,6 +98,12 @@ - Juniper - Kappa - Damu +- Cerise +- Stern +- Willow +- Esche +- Burnet +- Fennel - Link (Google Chromebook Pixel (2013)) - Mistral - Nyan @@ -100,13 +114,13 @@ - Hana (Lenovo N23 Yoga Chromebook) - Parrot (Acer C7/C710 Chromebook) - Peach Pit (Samsung Chromebook 2 11\") -- Atlas +- Atlas (Google Pixelbook Go) - Poppy - Nami -- Nautilus -- Nocturne -- Rammus -- Soraka +- Nautilus (Samsung Chromebook Plus (V2 / LTE)) +- Nocturne (Google Pixel Slate) +- Rammus (Asus Chromebook C425, Flip C433, Flip C434) +- Soraka (HP Chromebook x2) - Banjo (Acer Chromebook 15 (CB3-531)) - Candy (Dell Chromebook 11 3120) - Clapper (Lenovo N20 Chromebook) @@ -138,10 +152,11 @@ - Smaug (Google Pixel C) - Storm (OnHub Router TGR1900) - Stout (Lenovo Thinkpad X131e Chromebook) -- Trogdor -- Lazor - Bubs - Coachz +- Lazor +- Pompom +- Trogdor - Veyron_Jaq (Haier Chromebook 11) - Veyron_Jerry (Hisense Chromebook 11) - Veyron_Mighty (Haier Chromebook 11(edu)) @@ -149,11 +164,22 @@ - Veyron_Speedy (ASUS C201 Chromebook) - Veyron_Mickey (Asus Chromebit CS10) - Veyron_Rialto +- Dalboz +- Vilboz +- Ezkinil +- Morphius +- Trembyle +- Berknip +- Woomax +- Dirinboz +- Shuboz ## HP - Z220 SFF Workstation ## Intel +- Alderlake-P RVP +- Alderlake-P RVP with Chrome EC - Basking Ridge CRB - Cannonlake U LPDDR4 RVP - Cannonlake Y LPDDR4 RVP @@ -206,6 +232,7 @@ - ThinkPad X1 - ThinkPad X230 - ThinkPad X230t +- ThinkPad X230s - ThinkPad X60 / X60s / X60t ## OpenCellular @@ -226,6 +253,7 @@ ## Supermicro - X11SSH-TF - X11SSM-F +- X11SSH-F ## UP - Squared diff --git a/MAINTAINERS b/MAINTAINERS index 9a31a3f646..6a1f500de7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -511,7 +511,6 @@ M: David Guckian S: Odd Fixes F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ -F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/ INTEL FSP 1.1 M: Lee Leahy @@ -529,6 +528,14 @@ F: src/drivers/intel/fsp2_0/ # Systems on a Chip ################################################################################ +AMD Picasso +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +S: Maintained +F: src/soc/amd/picasso +F: src/vendorcode/amd/fsp/picasso + INTEL APOLLOLAKE_SOC M: Andrey Petrov S: Maintained diff --git a/Makefile.inc b/Makefile.inc index 69ac747800..9273961570 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -35,7 +35,8 @@ COREBOOT_EXPORTS += KERNELVERSION # Basic component discovery MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) -COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR +CARRIER_DIR:=$(call strip_quotes,$(CONFIG_CARRIER_DIR)) +COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR CARRIER_DIR ## Final build results, which CBFSTOOL uses to create the final ## rom image file, are placed under $(objcbfs). @@ -1134,22 +1135,6 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif -ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - @printf " SeaBIOS Thread optionroms\n" - $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) diff --git a/configs/config.scaleway_tagada b/configs/config.scaleway_tagada new file mode 100644 index 0000000000..eaa428831b --- /dev/null +++ b/configs/config.scaleway_tagada @@ -0,0 +1,15 @@ +CONFIG_VENDOR_SCALEWAY=y +CONFIG_BOARD_SCALEWAY_TAGADA=y +CONFIG_CBFS_SIZE=0x400000 +CONFIG_CONSOLE_POST=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_IQAT_ENABLE is not set +CONFIG_LEGACY_UART_MODE=y +CONFIG_USE_DENVERTON_NS_FSP_CAR=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd" +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_BOOT_STATE=y diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index da199e4bd3..6208578b74 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -106,6 +106,31 @@ bootorder-file := $(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)) bootorder-type := raw endif +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +ifneq ($(CONFIG_UPDATE_IMAGE),y) +INTERMEDIATE+=seabios_ps2_timeout +seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup +endif +endif +endif + +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +INTERMEDIATE+=seabios_sercon +seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Add sercon-port file\n" +# $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port +endif + +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +INTERMEDIATE+=seabios_thread_optionroms +seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Thread optionroms\n" + $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 50d013dbaf..84bad55371 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -159,7 +159,7 @@ static u8 i8042_wait_cmd_rdy(void) */ static u8 i8042_wait_data_rdy(void) { - int retries = 10000; + int retries = 30000; while (retries-- && !(read_status() & OBF)) udelay(50); diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index f70b23ff5b..2f06be1a2c 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dptf.c ramstage-y += acpigen_dsm.c @@ -15,6 +16,8 @@ ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c +postcar-y += acpi_pm.c + ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c endif diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 15ac9f9ce1..795a2f84df 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1251,14 +1251,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) /* should be 0 ACPI 3.0 */ fadt->reserved = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) - fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) - fadt->preferred_pm_profile = PM_TABLET; - else - fadt->preferred_pm_profile = PM_DESKTOP; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); arch_fill_fadt(fadt); @@ -1626,7 +1619,7 @@ void *acpi_find_wakeup_vector(void) void *wake_vec; int i; - if (!acpi_is_wakeup()) + if (!acpi_is_wakeup_s3()) return NULL; printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n"); diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c new file mode 100644 index 0000000000..540b6d2bee --- /dev/null +++ b/src/acpi/acpi_pm.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* This is filled with acpi_handoff_wakeup_s3() call early in ramstage. */ +static int acpi_slp_type = -1; + +static void acpi_handoff_wakeup(void) +{ + if (acpi_slp_type < 0) { + if (romstage_handoff_is_resume()) { + printk(BIOS_DEBUG, "S3 Resume\n"); + acpi_slp_type = ACPI_S3; + } else { + printk(BIOS_DEBUG, "Normal boot\n"); + acpi_slp_type = ACPI_S0; + } + } +} + +int acpi_handoff_wakeup_s3(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S3); +} + +void __weak mainboard_suspend_resume(void) +{ +} + +/* Default mapping to ACPI FADT preferred_pm_profile field. */ +uint8_t acpi_get_preferred_pm_profile(void) +{ + switch (smbios_mainboard_enclosure_type()) { + case SMBIOS_ENCLOSURE_LAPTOP: + case SMBIOS_ENCLOSURE_CONVERTIBLE: + return PM_MOBILE; + case SMBIOS_ENCLOSURE_DETACHABLE: + case SMBIOS_ENCLOSURE_TABLET: + return PM_TABLET; + case SMBIOS_ENCLOSURE_DESKTOP: + return PM_DESKTOP; + case SMBIOS_ENCLOSURE_UNKNOWN: + default: + return PM_UNSPECIFIED; + } +} diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 900c9c1e10..b5e52e6ecf 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -88,16 +88,6 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 && SMP -config X86_RESET_VECTOR - hex - depends on ARCH_X86 - default 0xfffffff0 - help - Specify the location of the x86 reset vector. In traditional devices - this must match the architectural reset vector to produce a bootable - image. Nontraditional designs may use this to position the reset - vector into its desired location. - config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a5c330905a..5157564847 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -158,7 +158,6 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-y += boot.c romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C @@ -202,7 +201,6 @@ $(eval $(call create_class_compiler,postcar,x86_64)) endif postcar-generic-ccopts += -D__POSTCAR__ -postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += post.c postcar-y += gdt_init.S diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 2802bd32ab..43a68f95f4 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -8,45 +8,6 @@ #include #include #include -#include - -#if ENV_RAMSTAGE || ENV_POSTCAR - -/* This is filled with acpi_is_wakeup() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_is_wakeup(void) -{ - acpi_handoff_wakeup(); - /* Both resume from S2 and resume from S3 restart at CPU reset */ - return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); -} - -int acpi_is_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - -int acpi_is_wakeup_s4(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S4); -} -#endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 @@ -55,22 +16,6 @@ asmlinkage void (*acpi_do_wakeup)(uintptr_t vector) = (void *)WAKEUP_BASE; extern unsigned char __wakeup; extern unsigned int __wakeup_size; -static void acpi_jump_to_wakeup(void *vector) -{ - /* Copy wakeup trampoline in place. */ - memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); - - set_boot_successful(); - - timestamp_add_now(TS_ACPI_WAKE_JUMP); - - acpi_do_wakeup((uintptr_t)vector); -} - -void __weak mainboard_suspend_resume(void) -{ -} - void __noreturn acpi_resume(void *wake_vec) { /* Restore GNVS pointer in SMM if found. */ @@ -79,8 +24,15 @@ void __noreturn acpi_resume(void *wake_vec) /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); + /* Copy wakeup trampoline in place. */ + memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + + set_boot_successful(); + + timestamp_add_now(TS_ACPI_WAKE_JUMP); + post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); + acpi_do_wakeup((uintptr_t)wake_vec); die("Failed the jump to wakeup vector\n"); } diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index eabe87380a..641d8923bf 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -11,18 +11,17 @@ /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; + . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ -#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 12K) #endif - /* Vboot measured boot TCPA log measurements. - * Needs to be transferred until CBMEM is available - */ #if CONFIG(TPM_MEASURED_BOOT) + /* Vboot measured boot TCPA log measurements. + * Needs to be transferred until CBMEM is available */ TPM_TCPA_LOG(., 2K) #endif /* Stack for CAR stages. Since it persists across all stages that @@ -33,8 +32,8 @@ _ecar_stack = .; /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that - * multiple stages (romstage and verstage) have a consistent - * link address of these shared objects. */ + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG(PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); @@ -55,8 +54,8 @@ _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + . += 80; + _ecar_ehci_dbg_info = .; /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -110,7 +109,7 @@ _rom_mtrr_base = _rom_mtrr_mask; . = 0xffffff00; .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index ea8d7e9dbd..b69a8dc1a5 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { KEEP(*(.id)) } diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 3659cc9f96..cbf887cc1c 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,7 +28,7 @@ SECTIONS #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, + BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 19b6f5d989..dc676cf141 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1068,7 +1068,7 @@ static int smbios_write_type17(unsigned long *current, int *handle, int type16) return totallen; } -static int smbios_write_type19(unsigned long *current, int *handle) +static int smbios_write_type19(unsigned long *current, int *handle, int type16) { struct smbios_type19 *t = (struct smbios_type19 *)*current; int len = sizeof(struct smbios_type19); @@ -1084,6 +1084,7 @@ static int smbios_write_type19(unsigned long *current, int *handle) t->type = SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS; t->length = len - 2; t->handle = *handle; + t->memory_array_handle = type16; for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { if (meminfo->dimm[i].dimm_size > 0) { @@ -1335,7 +1336,7 @@ unsigned long smbios_write_tables(unsigned long current) const int type16 = handle; update_max(len, max_struct_size, smbios_write_type16(¤t, &handle)); update_max(len, max_struct_size, smbios_write_type17(¤t, &handle, type16)); - update_max(len, max_struct_size, smbios_write_type19(¤t, &handle)); + update_max(len, max_struct_size, smbios_write_type19(¤t, &handle, type16)); update_max(len, max_struct_size, smbios_write_type32(¤t, handle++)); update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index dd352adaaa..a5721506d0 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -52,6 +52,8 @@ enum timestamp_id { TS_SELFBOOT_JUMP = 99, TS_START_POSTCAR = 100, TS_END_POSTCAR = 101, + TS_DELAY_START = 110, + TS_DELAY_END = 111, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -177,6 +179,8 @@ static const struct timestamp_id_to_name { { TS_LOAD_PAYLOAD, "load payload" }, { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, { TS_SELFBOOT_JUMP, "selfboot jump" }, + { TS_DELAY_START, "Forced delay start" }, + { TS_DELAY_END, "Forced delay end" }, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index de5bcdcad0..942539cac2 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -52,7 +52,7 @@ static void model_14_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index c2406d850c..83efb44693 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -51,7 +51,7 @@ static void model_15_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2f4fd63a7a..c1c75775e0 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -49,7 +49,7 @@ static void model_16_init(struct device *dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) + if (acpi_is_wakeup_s3()) restore_mtrr(); x86_mtrr_check(); diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index b90dd04992..e00e0b41f8 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* _RESET_VECTOR: typically the top of the ROM */ +/* + * _ROMTOP : The top of the ROM used where we + * need to put the reset vector. + */ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - - . = CONFIG_X86_RESET_VECTOR; + _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + _ROMTOP = 0xfffffff0; + . = _ROMTOP; .reset . : { *(.reset); . = 15; diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index fc1e1b3062..876fde6733 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -209,6 +209,12 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size, smm_stub_size = rmodule_memory_size(&smm_stub); stub_entry_offset = rmodule_entry_offset(&smm_stub); + if (smm_stub_size > params->per_cpu_save_state_size) { + printk(BIOS_ERR, "SMM Module: SMM stub size larger than save state size\n"); + printk(BIOS_ERR, "SMM Module: Staggered entry points will overlap stub\n"); + return -1; + } + /* Assume the stub is always small enough to live within upper half of * SMRAM region after the save state space has been allocated. */ smm_stub_loc = &base[SMM_ENTRY_OFFSET]; diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index 22f336ec8d..14ed9b89eb 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -134,6 +134,12 @@ static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, return 0; } + if (stub_size > ss_size) { + printk(BIOS_ERR, "%s: Save state larger than SMM stub size\n", __func__); + printk(BIOS_ERR, " Decrease stub size or increase the size allocated for the save state\n"); + return 0; + } + for (i = 0; i < num_cpus; i++) { cpus[i].smbase = base; cpus[i].entry = base + smm_entry_offset; @@ -407,12 +413,14 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size, * for default handler, but for relocated handler it lives at the beginning * of SMRAM which is TSEG base */ - size = params->num_concurrent_stacks * params->per_cpu_stack_size; - stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params); + const size_t total_stack_size = params->num_concurrent_stacks * + params->per_cpu_stack_size; + stacks_top = smm_stub_place_stacks((char *)params->smram_start, total_stack_size, + params); if (stacks_top == NULL) { printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__); printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__, - base, size); + base, total_stack_size); return -1; } params->stack_top = stacks_top; @@ -440,8 +448,8 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size, stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; - printk(BIOS_DEBUG, "%s: stack_end = 0x%x\n", - __func__, stub_params->runtime.smbase); + printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", + __func__, stub_params->stack_top - total_stack_size); printk(BIOS_DEBUG, "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", diff --git a/src/device/Kconfig b/src/device/Kconfig index 777f3f50d3..d564f00b9c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -534,9 +534,20 @@ config PCI_ALLOW_BUS_MASTER if PCI_ALLOW_BUS_MASTER +config PCI_SET_BUS_MASTER_PCI_BRIDGES + bool "PCI bridges" + default y + help + Let coreboot configure bus mastering for PCI bridges. Enabling bus + mastering for a PCI bridge also allows it to forward requests from + downstream devices. Currently, payloads ignore this and only enable + bus mastering for the downstream device. Hence, this option is needed + for compatibility until payloads are fixed. + config PCI_ALLOW_BUS_MASTER_ANY_DEVICE bool "Any devices" default y + select PCI_SET_BUS_MASTER_PCI_BRIDGES help Allow coreboot to enable PCI bus mastering for any device. The actual selection of devices depends on the various PCI drivers in coreboot. diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 6075ebeac7..a00897736a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -542,7 +542,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource) dev->command |= PCI_COMMAND_MEMORY; if (resource->flags & IORESOURCE_IO) dev->command |= PCI_COMMAND_IO; - if (resource->flags & IORESOURCE_PCI_BRIDGE) + if (resource->flags & IORESOURCE_PCI_BRIDGE && + CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES)) dev->command |= PCI_COMMAND_MASTER; } @@ -953,13 +954,16 @@ static void set_pci_ops(struct device *dev) if ((driver->vendor == dev->vendor) && device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; - printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", - dev_path(dev), driver->vendor, driver->device, - (driver->ops->scan_bus ? "bus " : "")); - return; + break; } } + if (dev->ops) { + printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev), + driver->vendor, driver->device, (driver->ops->scan_bus ? "bus " : "")); + return; + } + /* If I don't have a specific driver use the default operations. */ switch (dev->hdr_type & 0x7f) { /* Header type */ case PCI_HEADER_TYPE_NORMAL: @@ -1128,7 +1132,8 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus, dev->class = class >> 8; /* Architectural/System devices always need to be bus masters. */ - if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) + if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM && + CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) dev->command |= PCI_COMMAND_MASTER; /* diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index b5f794bcb6..bf974ffffe 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -2,6 +2,8 @@ /* * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ + +#include #include #include diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index b6e8e91d23..e644d910f7 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -2,6 +2,7 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 +#include #include #include "ast_drv.h" diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 3181e7a0cf..c0212c3e27 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -419,6 +419,15 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, /* Read to clear INTR_STAT_STOP_DET */ read32(®s->clear_stop_det_intr); + /* Check TX abort */ + if (read32(®s->raw_intr_stat) & INTR_STAT_TX_ABORT) { + printk(BIOS_ERR, "I2C TX abort detected (%08x)\n", + read32(®s->tx_abort_source)); + /* clear INTR_STAT_TX_ABORT */ + read32(®s->clear_tx_abrt_intr); + goto out; + } + /* Wait for the bus to go idle */ if (dw_i2c_wait_for_bus_idle(regs)) { printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); @@ -747,8 +756,8 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) write32(®s->rx_thresh, 0); write32(®s->tx_thresh, 0); - /* Enable stop detection interrupt */ - write32(®s->intr_mask, INTR_STAT_STOP_DET); + /* Enable stop detection and TX abort interrupt */ + write32(®s->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT); printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index 45f305e3b2..e20a5d1d7e 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -17,7 +17,7 @@ /* * Timing values are in units of clock period, with the clock speed - * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ + * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ * Automatic configuration is done based on requested speed, but the * values may need tuned depending on the board and the number of * devices present on the bus. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 2b8b9b28f0..210444ebc4 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -198,7 +198,6 @@ static void rx6110sa_fill_ssdt(const struct device *dev) /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_string("_HID", RX6110SA_HID_NAME); acpigen_write_name_string("_DDN", RX6110SA_HID_DESC); acpigen_write_STA(acpi_device_status(dev)); diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 557a7489a1..fc0109db2a 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -4,7 +4,6 @@ #define _I2C_RX6110SA_H_ #define RX6110SA_ACPI_NAME "ERX6" -#define RX6110SA_HID_NAME "RX6110SA" #define RX6110SA_HID_DESC "Real Time Clock" /* Register layout */ diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 4ff3705ad9..4321757705 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -424,11 +424,6 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, uint8_t *buf, size_t len) if (burstcnt > (len-1-count)) burstcnt = len-1-count; -#ifdef CONFIG_TPM_I2C_BURST_LIMITATION - if (burstcnt > CONFIG_TPM_I2C_BURST_LIMITATION) - burstcnt = CONFIG_TPM_I2C_BURST_LIMITATION; -#endif /* CONFIG_TPM_I2C_BURST_LIMITATION */ - if (iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality), &(buf[count]), burstcnt) == 0) count += burstcnt; diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 86d1f2f760..5fc100aa4b 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -4,7 +4,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) verstage-y += car.c verstage-y += fsp_util.c -verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580aac..3be9eb92df 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -133,7 +133,7 @@ CAR_init_done: jne halt2 /* Setup bootloader stack */ - movl %edx, %esp + movl $_ecar_stack, %esp /* * ebp: FSP_INFO_HEADER address diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index cd5af4ecfa..4440b81b5b 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -53,7 +53,7 @@ static void emit_sar_acpi_structures(const struct device *dev) /* Retrieve the sar limits data */ if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "Error: failed from getting SAR limits!\n"); + printk(BIOS_DEBUG, "failed from getting SAR limits!\n"); return; } diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 2ffccbc77c..ed7f97dc43 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1624,6 +1624,53 @@ int google_chromeec_ap_reset(void) return 0; } +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable) +{ + struct ec_params_regulator_enable params = { + .index = index, + .enable = enable, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_ENABLE, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) +{ + + struct ec_params_regulator_is_enabled params = { + .index = index, + }; + struct ec_response_regulator_is_enabled resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_IS_ENABLED, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *enabled = resp.enabled; + + return 0; +} + int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, uint32_t max_mv) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index bed8594a8b..c3c456ff14 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,8 +353,27 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); */ int google_chromeec_ap_reset(void); +/** + * Configure the regulator as enabled / disabled. + * + * @param index Regulator ID + * @param enable Set to enable / disable the regulator + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable); + +/** + * Query if the regulator is enabled. + * + * @param index Regulator ID + * @param *enabled If successful, enabled indicates enable/disable status. + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled); + /** * Set voltage for the voltage regulator within the range specified. + * * @param index Regulator ID * @param min_mv Minimum voltage * @param max_mv Maximum voltage @@ -365,6 +384,7 @@ int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, /** * Get the currently configured voltage for the voltage regulator. + * * @param index Regulator ID * @param *voltage_mv If successful, voltage_mv is filled with current voltage * @return 0 on success, -1 on error diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 241ec393c6..fb83d60443 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -1388,7 +1388,7 @@ enum ec_feature_code { */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, /* - * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option. * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should * be sent to RO to be precise. */ diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 5447cf66db..2bb8683a7f 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1077,6 +1077,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); +int acpi_handoff_wakeup_s3(void); /* ACPI_Sn assignments are defined to always equal the sleep state numbers */ enum { @@ -1104,6 +1105,8 @@ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt) } #endif +uint8_t acpi_get_preferred_pm_profile(void); + /* Returns ACPI_Sx values. */ int acpi_get_sleep_type(void); @@ -1122,24 +1125,16 @@ static inline int acpi_s3_resume_allowed(void) return CONFIG(HAVE_ACPI_RESUME); } -#if CONFIG(HAVE_ACPI_RESUME) - -#if ENV_ROMSTAGE_OR_BEFORE static inline int acpi_is_wakeup_s3(void) { - return (acpi_get_sleep_type() == ACPI_S3); -} -#else -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_s4(void); -#endif + if (!acpi_s3_resume_allowed()) + return 0; -#else -static inline int acpi_is_wakeup(void) { return 0; } -static inline int acpi_is_wakeup_s3(void) { return 0; } -static inline int acpi_is_wakeup_s4(void) { return 0; } -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + return (acpi_get_sleep_type() == ACPI_S3); + + return acpi_handoff_wakeup_s3(); +} static inline uintptr_t acpi_align_current(uintptr_t current) { diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 9acf794dec..6200fdedd6 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -47,35 +47,35 @@ union dimm_flags_ddr2_st { * We do not care how these bits are ordered */ struct { /* Module can work at 5.00V */ - unsigned operable_5_00V:1; + unsigned int operable_5_00V:1; /* Module can work at 3.33V */ - unsigned operable_3_33V:1; + unsigned int operable_3_33V:1; /* Module can work at 2.50V */ - unsigned operable_2_50V:1; + unsigned int operable_2_50V:1; /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ - unsigned operable_1_80V:1; + unsigned int operable_1_80V:1; /* Module can work at 1.50V */ - unsigned operable_1_50V:1; + unsigned int operable_1_50V:1; /* Module can work at 1.35V */ - unsigned operable_1_35V:1; + unsigned int operable_1_35V:1; /* Module can work at 1.20V */ - unsigned operable_1_25V:1; + unsigned int operable_1_25V:1; /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ - unsigned is_ecc:1; + unsigned int is_ecc:1; /* Supports weak driver */ - unsigned weak_driver:1; + unsigned int weak_driver:1; /* Supports terminating at 50 Ohm */ - unsigned terminate_50ohms:1; + unsigned int terminate_50ohms:1; /* Partial Array Self Refresh */ - unsigned pasr:1; + unsigned int pasr:1; /* Supports burst length 8 */ - unsigned bl8:1; + unsigned int bl8:1; /* Supports burst length 4 */ - unsigned bl4:1; + unsigned int bl4:1; /* DIMM Package is stack */ - unsigned stacked:1; + unsigned int stacked:1; /* the assembly supports self refresh */ - unsigned self_refresh:1; + unsigned int self_refresh:1; }; unsigned int raw; }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 675acc4a1b..5095f1168a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -453,24 +453,21 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_GNB 0x15D0 -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 -#define PCI_DEVICE_ID_AMD_FAM17H_GPU 0x15D8 -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC -#define PCI_DEVICE_ID_AMD_FAM17H_HDA0 0x15DE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 -#define PCI_DEVICE_ID_AMD_FAM17H_DF0 0x15E8 -#define PCI_DEVICE_ID_AMD_FAM17H_DF1 0x15E9 -#define PCI_DEVICE_ID_AMD_FAM17H_DF2 0x15EA -#define PCI_DEVICE_ID_AMD_FAM17H_DF3 0x15EB -#define PCI_DEVICE_ID_AMD_FAM17H_DF4 0x15EC -#define PCI_DEVICE_ID_AMD_FAM17H_DF5 0x15ED -#define PCI_DEVICE_ID_AMD_FAM17H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3 0x15EB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 @@ -478,7 +475,10 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E -#define PCI_DEVICE_ID_AMD_FAM17H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 + +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/include/rules.h b/src/include/rules.h index d30b2b896a..6ebb37e804 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,10 +63,11 @@ /* * NOTE: "verstage" code may either run as a separate stage or linked into the - * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The - * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when - * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or - * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options). + * bootblock/romstage, depending on the setting of the VBOOT_SEPARATE_VERSTAGE + * kconfig option. The ENV_SEPARATE_VERSTAGE macro will only return true for + * "verstage" code when CONFIG(VBOOT_SEPARATE_VERSTAGE) is true, otherwise that + * code will have ENV_BOOTBLOCK or ENV_ROMSTAGE set (depending on the + * "VBOOT_STARTS_IN_"... kconfig options). */ #elif defined(__VERSTAGE__) #define ENV_DECOMPRESSOR 0 diff --git a/src/lib/asan.c b/src/lib/asan.c index 6de0de1409..cf91111ab2 100644 --- a/src/lib/asan.c +++ b/src/lib/asan.c @@ -8,6 +8,7 @@ * */ +#include #include #include #include diff --git a/src/lib/gnat/i-c.ads b/src/lib/gnat/i-c.ads index 1403fcec80..7e90a60e65 100644 --- a/src/lib/gnat/i-c.ads +++ b/src/lib/gnat/i-c.ads @@ -59,6 +59,9 @@ package Interfaces.C is type size_t is mod 2 ** System.Parameters.ptr_bits; + -- For convenience, also provide an uintptr_t type + type uintptr_t is mod 2 ** System.Parameters.ptr_bits; + ---------------------------- -- Characters and Strings -- ---------------------------- diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 3fe50c9bb6..173ee97192 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -444,7 +444,7 @@ void main(void) post_code(POST_ENTRY_RAMSTAGE); /* Handoff sleep type from romstage. */ - acpi_is_wakeup(); + acpi_is_wakeup_s3(); threads_initialize(); /* Schedule the static boot state entries. */ diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index b54619d8d8..0a7a822f7b 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -8,7 +8,7 @@ struct romstage_handoff { /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * CONFIG_RELOCATABLE_RAMSTAGE is enabled the chipset code is * responsible for initializing this variable. Otherwise, ramstage * will be re-loaded from cbfs (which can be slower since it lives * in flash). */ diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 8600c27df9..a69614fd47 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -51,6 +51,7 @@ #define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 #define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT2_PRESENT CONFIG(BOARD_ASUS_F2A85_M_PRO) GPIO_CONTROL f2a85_m_gpio[] = { {-1} diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 4e124f28e3..830d3a8bcd 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -111,7 +111,9 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) device pci 15.0 on end # PCI bridge device pci 15.1 on end # PCI bridge - device pci 15.2 on end # PCI bridge # Only present with the original boot firmware + # FIXME: serial console stops working when enabling resources + # for 15.2, and payloads hang + device pci 15.2 off end # PCI bridge end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/clevo/cml-u/Kconfig.name b/src/mainboard/clevo/cml-u/Kconfig.name index d5f867a475..f8f22cc531 100644 --- a/src/mainboard/clevo/cml-u/Kconfig.name +++ b/src/mainboard/clevo/cml-u/Kconfig.name @@ -1,2 +1,4 @@ +comment "Comet Lake U" + config BOARD_CLEVO_L140CU - bool "L140CU" + bool "L140CU / L141CU" diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig new file mode 100644 index 0000000000..ed0600a018 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_CLEVO_N130WU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT +# select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config MAINBOARD_DIR + string + default "clevo/kbl-u" + +config VARIANT_DIR + string + default "n13xwu" if BOARD_CLEVO_N130WU + +config MAINBOARD_PART_NUMBER + string + default "N130WU" if BOARD_CLEVO_N130WU + +config CBFS_SIZE + hex + default 0x600000 if BOARD_CLEVO_N130WU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd" if VBOOT && !VBOOT_SLOTS_RW_A + # TODO +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,5917" if BOARD_CLEVO_N130WU + +config PXE_ROM_ID + string + default "10ec,8168" + +config UART_FOR_CONSOLE + int + default 2 + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +config LINEAR_FRAMEBUFFER_MAX_WIDTH + int + default 1920 + +config LINEAR_FRAMEBUFFER_MAX_HEIGHT + int + default 1080 + +endif diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name new file mode 100644 index 0000000000..5a6f699c67 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "Kaby Lake U" + +config BOARD_CLEVO_N130WU + bool "N130WU / N131WU" diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc new file mode 100644 index 0000000000..b424d4da19 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/clevo/kbl-u/acpi/ec.asl b/src/mainboard/clevo/kbl-u/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/clevo/kbl-u/acpi/superio.asl b/src/mainboard/clevo/kbl-u/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/clevo/kbl-u/board_info.txt b/src/mainboard/clevo/kbl-u/board_info.txt new file mode 100644 index 0000000000..97514fc003 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Clevo +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/kbl-u/bootblock.c b/src/mainboard/clevo/kbl-u/bootblock.c new file mode 100644 index 0000000000..067c9ecab2 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_gpios(); +} diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl new file mode 100644 index 0000000000..21acf37dc2 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + + Device (\_SB.PCI0) { + #include + #include + } + + #include +} diff --git a/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h new file mode 100644 index 0000000000..ef2a21c418 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c new file mode 100644 index 0000000000..b5d67864a0 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * TODO: + * - Add kill switches for WLAN, BT, LTE, CCD + * - Add support for WoL (LAN, WLAN) + * - Make M.2 port configurable (SATA <> PCIe) + * - Make SATA DevSlp configurable + * - Make TBT port configurable (TBT <> DisplayPort) + */ + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + mainboard_configure_gpios(); +} diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c new file mode 100644 index 0000000000..1399d33608 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt new file mode 100644 index 0000000000..30f8ce6e3f --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt @@ -0,0 +1 @@ +Board name: N130WU / N131WU diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt new file mode 100644 index 0000000000..f88aef4c04 Binary files /dev/null and b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt differ diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb new file mode 100644 index 0000000000..55c5a69b52 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" # T3 + register "gpu_pp_down_delay_ms" = " 0" # T10 + register "gpu_pp_cycle_delay_ms" = "500" # T12 + register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 + register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 + + register "gpu_pch_backlight_pwm_hz" = "200" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # FSP Configuration + register "SkipExtGfxScan" = "1" + register "SaGv" = "SaGv_Enabled" + register "eist_enable" = "1" + + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1558 0x1313 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 on end # Gaussian Mixture Model + device pci 13.0 off end # Sensor Hub + device pci 14.0 on # USB xHCI + register "SsicPortEnable" = "0" + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera + device pci 15.0 off end # I2C0 + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "0" + # Ports + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 on end # UART 2 + device pci 19.1 off end # I2C5 + device pci 19.2 off end # I2C4 + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on end # x4 TBT + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpLtrEnable[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 WLAN + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpLtrEnable[5]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M (J_SSD1) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDXC + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 on # Power Management Controller + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + end + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Trace Hub + end +end diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd new file mode 100644 index 0000000000..f53cdf4e47 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd @@ -0,0 +1,32 @@ +FLASH 8M { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + WP_RO@0x2d000 0x5d3000 { + FMAP@0x0 0x800 + RO_VPD(PRESERVE)@0x800 0x4000 + RO_SECTION@0x4800 0x5ce800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x58e000 + } + } + } +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads new file mode 100644 index 0000000000..38abb7aae9 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c new file mode 100644 index 0000000000..e7aadcccfc --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c @@ -0,0 +1,503 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + // RCIN# + _PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0), + + // LAD0 + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0), + + // LAD1 + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0), + + // LAD2 + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0), + + // LAD3 + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0), + + // LFRAME# + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + + // SERIRQ + _PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0), + + // PIRQA# + _PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0), + + // CLKRUN# + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + + // CLKOUT_LPC0 + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + + // CLKOUT_LPC1 + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + + // PME# + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + + // BM_BUSY# + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + + // SUSWARN#/SUSPWRDNACK + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + + // SUS_STAT#/ESPI_RESET# + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + + // SUS_ACK# + _PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0), + + // SD_1P8_SEL + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + + // SD_PWR_EN# + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + + // ISH_GP0 + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + + // ISH_GP1 + _PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0), + + // ISH_GP2 + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + + // ISH_GP3 + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + + // ISH_GP4 + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + + // ISH_GP5 + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + + // CORE_VID0 + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + + // CORE_VID1 + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + + // VRALERT# + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + + // CPU_GP2 + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + + // CPU_GP3 + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + + // SRCCLKREQ0# + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + + // SRCCLKREQ1# + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + + // SRCCLKREQ2# + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + + // SRCCLKREQ3# + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + + // SRCCLKREQ4# + _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + + // SRCCLKREQ5# + _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + + // EXT_PWR_GATE# + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + + // SLP_S0# + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + + // PLTRST# + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + + // SPKR + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + + // GSPI0_CS# + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + + // GSPI0_CLK + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + + // GSPI0_MISO + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + + // GSPI0_MOSI + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + + // GSPI1_CS# + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + + // GSPI1_CLK + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + + // GSPI1_MISO + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + + // GSPI1_MOSI + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + + // SML1ALERT#/PCHHOT# + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + + // SMBCLK + _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), + + // SMBDATA + _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), + + // SMBALERT# + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + + // SML0CLK + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + + // SML0DATA + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + + // SML0ALERT# + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + + // SML1CLK +// _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), + + // SML1DATA +// _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), + + // UART0_RXD + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + + // UART0_TXD + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + + // UART0_RTS# + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + + // UART0_CTS# + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + + // UART1_RXD + _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), + + // UART1_TXD + _PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0), + + // UART1_RTS# + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + + // UART1_CTS# + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + + // I2C0_SDA + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + + // I2C0_SCL + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + + // I2C1_SDA + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + + // I2C1_SCL + _PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0), + + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + + // UART2_RTS# + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + + // UART2_CTS# + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + + // SPI1_CS# + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + + // SPI1_CLK + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + + // SPI1_MISO + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + + // SPI1_MOSI + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + + // FLASHTRIG + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + + // ISH_I2C0_SDA + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + + // ISH_I2C0_SCL + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + + // ISH_I2C1_SDA + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + + // ISH_I2C1_SCL + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + + // ISH_UART0_RXD + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + + // ISH_UART0_TXD + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + + // ISH_UART0_RTS# + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + + // ISH_UART0_CTS# + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + + // DMIC_CLK1 + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + + // DMIC_DATA1 + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + + // DMIC_CLK0 + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + + // DMIC_DATA0 + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + + // SPI1_IO2 + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0), + + // SPI1_IO3 + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + + // I2S_MCLK + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + + // SATAXPCIE0/SATAGP0 + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + + // SATAXPCIE1/SATAGP1 + _PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0), + + // SATAXPCIE2/SATAGP2 + _PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0), + + // CPU_GP0 + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + + // DEVSLP0 + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + + // DEVSLP1 + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + + // DEVSLP2 + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + + // CPU_GP1 + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + + // SATALED# + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + + // USB2_OC0# + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + + // USB2_OC1# + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + + // USB2_OC2# + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + + // USB2_OC3# + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + + // DDPB_HPD0 + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + + // DDPC_HPD1 + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + + // DDPD_HPD2 + _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), + + // DDPE_HPD3 + _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), + + // EDP_HPD + _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + + // DDPB_CTRLCLK + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + + // DDPB_CTRLDATA + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + + // DDPC_CTRLCLK + _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), + + // DDPC_CTRLDATA + _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), + + // DDPD_CTRLCLK + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + + // DDPD_CTRLDATA + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + + // BATLOW# + _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + + // LAN_WAKE# + _PAD_CFG_STRUCT(GPD2, 0x880502, 0x0), + + // PWRBTN# + _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + + // SLP_S3# + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + + // SLP_S4# + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + + // SLP_A# + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + + // RSVD + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + + // SUSCLK + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + + // SLP_WLAN# + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + + // SLP_S5# + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + + // I2S2_SCLK + _PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0), + + // I2S2_SFRM + _PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0), + + // I2S2_TXD + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + + // I2S2_RXD + _PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0), + + // I2C2_SDA + _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + + // I2C2_SCL + _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + + // I2C3_SDA + _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), + + // I2C3_SCL + _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), + + // I2C4_SDA + _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), + + // I2C4_SCL + _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), + + // I2C5_SDA/ISH_I2C2_SDA + _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), + + // I2C5_SCL/ISH_I2C2_SCL + _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), + + // EMMC_CMD + _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + + // EMMC_DATA0 + _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + + // EMMC_DATA1 + _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + + // EMMC_DATA2 + _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + + // EMMC_DATA3 + _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + + // EMMC_DATA4 + _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + + // EMMC_DATA5 + _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + + // EMMC_DATA6 + _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + + // EMMC_DATA7 + _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + + // EMMC_RCLK + _PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0), + + // EMMC_CLK + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + + // SD_CMD + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + + // SD_DATA0 + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0), + + // SD_DATA1 + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + + // SD_DATA2 + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + + // SD_DATA3 + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + + // SD_CD# + _PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), + + // SD_CLK + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + + // SD_WP + _PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0) +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c new file mode 100644 index 0000000000..00246a42e5 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0) +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c new file mode 100644 index 0000000000..05bb273a74 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek ALC269VC */ + 0x10ec0269, + 0x15581314, + 11, + AZALIA_SUBVENDOR(0, 0x15581314), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel iGPU HDMI */ + 0x8086280b, + 0x80860101, + 4, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x5, 0x18560010), + AZALIA_PIN_CFG(2, 0x6, 0x18560010), + AZALIA_PIN_CFG(2, 0x7, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index fcf50a9bd0..1af2e02adb 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include "../qemu-i440fx/fw_cfg.h" diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 02fb8300e0..601b485555 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -11,6 +11,7 @@ verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c romstage-y += chromeos.c +romstage-y += regulator.c romstage-y += romstage.c romstage-y += sdram_configs.c @@ -19,3 +20,4 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c +ramstage-y += regulator.c diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 8699ede772..e00eb2fde4 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include "gpio.h" @@ -14,7 +15,15 @@ #define MSDC0_DRV_MASK 0x3fffffff #define MSDC1_DRV_MASK 0x3ffff000 #define MSDC0_DRV_VALUE 0x24924924 -#define MSDC1_DRV_VALUE 0x24924000 +#define MSDC1_DRV_VALUE 0x1b6db000 + +#define MSDC1_GPIO_MODE0_BASE 0x10005360 +#define MSDC1_GPIO_MODE0_MASK 0x77777000 +#define MSDC1_GPIO_MODE0_VALUE 0x11111000 + +#define MSDC1_GPIO_MODE1_BASE 0x10005370 +#define MSDC1_GPIO_MODE1_MASK 0x7 +#define MSDC1_GPIO_MODE1_VALUE 0x1 static void register_reset_to_bl31(void) { @@ -57,6 +66,9 @@ static void configure_emmc(void) static void configure_sdcard(void) { void *gpio_base = (void *)IOCFG_RM_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + uint8_t enable = 1; int i; const gpio_t sdcard_pu_pin[] = { @@ -75,8 +87,17 @@ static void configure_sdcard(void) for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - /* set sdcard cmd/dat/clk pins driving to 10mA */ + /* set sdcard cmd/dat/clk pins driving to 8mA */ clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); + + mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c new file mode 100644 index 0000000000..d57df0126d --- /dev/null +++ b/src/mainboard/google/asurada/regulator.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static int get_mt6360_regulator_id(enum mtk_regulator regulator) +{ + switch (regulator) { + case MTK_REGULATOR_VDD2: + return MT6360_BUCK1; + case MTK_REGULATOR_VDDQ: + return MT6360_LDO7; + case MTK_REGULATOR_VMDDR: + return MT6360_LDO6; + case MTK_REGULATOR_VCC: + return MT6360_LDO5; + case MTK_REGULATOR_VCCQ: + return MT6360_LDO3; + default: + break; + } + + return -1; +} + +static int get_mt6359p_regulator_id(enum mtk_regulator regulator) +{ + switch (regulator) { + case MTK_REGULATOR_VCORE: + return MT6359P_GPU11; + default: + break; + } + + return -1; +} + +void mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + /* + * Handle the regulator that does not have a regulator ID + * in its underlying implementation. + */ + if (regulator == MTK_REGULATOR_VDD1) { + mt6359p_set_vm18_voltage(voltage_uv); + return; + } + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + uint32_t voltage_mv = voltage_uv / 1000; + google_chromeec_regulator_set_voltage(id, voltage_mv, voltage_mv); + return; + } + + id = get_mt6359p_regulator_id(regulator); + if (id >= 0) { + mt6359p_buck_set_voltage(id, voltage_uv); + return; + } + + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); +} + +uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + /* + * Handle the regulator that does not have a regulator ID + * in its underlying implementation. + */ + if (regulator == MTK_REGULATOR_VDD1) + return mt6359p_get_vm18_voltage(); + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + uint32_t voltage_mv = 0; + google_chromeec_regulator_get_voltage(id, &voltage_mv); + return voltage_mv * 1000; + } + + id = get_mt6359p_regulator_id(regulator); + if (id >= 0) + return mt6359p_buck_get_voltage(id); + + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); + + return 0; +} + +int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable) +{ + /* Return 0 if the regulator is already enabled or disabled. */ + if (mainboard_regulator_is_enabled(regulator) == enable) + return 0; + + int id; + + id = get_mt6360_regulator_id(regulator); + if (id < 0) { + printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator); + return -1; + } + + return google_chromeec_regulator_enable(id, enable); +} + +uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator) +{ + int id; + + id = get_mt6360_regulator_id(regulator); + if (id < 0) { + printk(BIOS_WARNING, "Invalid regulator ID: %d\n; assuming disabled", + regulator); + return 0; + } + + uint8_t enabled; + if (google_chromeec_regulator_is_enabled(id, &enabled) < 0) { + printk(BIOS_WARNING, + "Failed to query regulator ID: %d\n; assuming disabled", + regulator); + return 0; + } + + return enabled; +} diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c index a0e0818e01..47c1fb2268 100644 --- a/src/mainboard/google/asurada/romstage.c +++ b/src/mainboard/google/asurada/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include /* This must be defined in chromeos.fmd in same name and size. */ #define CALIBRATION_REGION "RW_DDR_TRAINING" @@ -43,6 +44,7 @@ static struct dramc_param_ops dparam_ops = { void platform_romstage_main(void) { + mt6359p_romstage_init(); mt_mem_init(&dparam_ops); mtk_mmu_after_dram(); } diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 891b48acc9..6c4f456565 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER default "Wheelie" if BOARD_GOOGLE_WHEELIE default "Magolor" if BOARD_GOOGLE_MAGOLOR default "Metaknight" if BOARD_GOOGLE_METAKNIGHT + default "Lantis" if BOARD_GOOGLE_LANTIS config MAX_CPUS int @@ -125,5 +126,6 @@ config VARIANT_DIR default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR default "metaknight" if BOARD_GOOGLE_METAKNIGHT + default "lantis" if BOARD_GOOGLE_LANTIS endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 31495a1552..2a8950c88e 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -72,3 +72,9 @@ config BOARD_GOOGLE_METAKNIGHT bool "-> Metaknight" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_LANTIS + bool "-> Lantis" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 0e21c4c91b..ade48661c5 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -7,13 +7,15 @@ FLASH@0xff000000 0x1000000 { RW_LEGACY(CBFS)@0x0 0x100000 RW_SECTION_A@0x100000 0x3a4800 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x3a27c0 - RW_FWID_A@0x3a47c0 0x40 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } RW_SECTION_B@0x4a4800 0x3a4800 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x3a27c0 - RW_FWID_B@0x3a47c0 0x40 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd index 60ea3ded64..4b318610cd 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd @@ -10,13 +10,15 @@ FLASH@0xfe000000 0x2000000 { RW_LEGACY(CBFS)@0x0 0xf00000 RW_SECTION_A@0xf00000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x23ffc0 + RW_FWID_A@0x24ffc0 0x40 + ME_RW_A(CBFS)@0x250000 0x190000 } RW_SECTION_B@0x12e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x23ffc0 + RW_FWID_B@0x24ffc0 0x40 + ME_RW_B(CBFS)@0x250000 0x190000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h new file mode 100644 index 0000000000..27c930d4f2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc new file mode 100644 index 0000000000..f6282bf04c --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt new file mode 100644 index 0000000000..856d016914 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt new file mode 100644 index 0000000000..26c06b6f40 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb new file mode 100644 index 0000000000..2933b1a354 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -0,0 +1,150 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | | + #| I2C2 | Touchscreen | + #| I2C3 | | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Discrete Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.1 off end #I2C 1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 15.3 off end #I2C 3 + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index d5903f6f8e..d455a47e32 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -64,6 +64,41 @@ chip soc/intel/jasperlake end end # USB xHCI device pci 15.0 on end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 2 device pci 15.3 off end # I2C 3 end end diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index d21e86792d..e697379965 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 835a8aae3a..7cc920d7ee 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -1,4 +1,11 @@ chip soc/intel/cannonlake + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -205,29 +212,30 @@ chip soc/intel/cannonlake chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, + .thresholds={TEMP_PCT(70, 100), + TEMP_PCT(66, 90), + TEMP_PCT(62, 80), + TEMP_PCT(58, 70), + TEMP_PCT(53, 60), + TEMP_PCT(48, 50), + TEMP_PCT(43, 40), + TEMP_PCT(38, 30),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, @@ -236,7 +244,7 @@ chip soc/intel/cannonlake .granularity = 200,}" register "controls.power_limits.pl2" = "{ .min_power = 25000, - .max_power = 64000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" @@ -394,8 +402,11 @@ chip soc/intel/cannonlake register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 3b247e9fad..d641405daa 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index ccb5c0599b..f50f8f23a0 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -16,6 +16,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A19, NONE), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 6ec1a48add..3b094a34a8 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -69,6 +69,19 @@ chip soc/intel/cannonlake register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # The Linux Kernel does not allow an inverted BOTH_EDGE irq + # So we need to use GpioIO() instead of GpioInt() + # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 564c18c76b..cf9344ee5a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 6c7547c21a..04ae7db8f9 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -69,7 +69,7 @@ static const int *adc_voltages[] = { static uint32_t get_adc_index(unsigned int channel) { - int value = auxadc_get_voltage(channel); + int value = auxadc_get_voltage_uv(channel); assert(channel < ARRAY_SIZE(adc_voltages)); const int *voltages = adc_voltages[channel]; diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 268b7caf65..cbcb5da1c6 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -91,7 +91,7 @@ static void power_on_panel(struct panel_description *panel) gpio_output(GPIO_PPVARN_LCD_EN, 1); gpio_output(GPIO_PP1800_LCM_EN, 1); gpio_output(GPIO_PP3300_LCM_EN, 1); - mdelay(6); + mdelay(15); gpio_output(GPIO_LCM_RST_1V8, 1); mdelay(6); } diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 662e6af8d6..3c7187e048 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -210,6 +210,20 @@ chip soc/intel/apollolake register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 3e482a9f27..6faca2b133 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index aac160bc06..6b267c90cc 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -138,6 +138,13 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "K4F8E3S4HD-MGCL", }, + /* NT6AN256T32AV-J2 - both logical channels */ + [9] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "NT6AN256T32AV-J2", + }, }; static const struct lpddr4_cfg lp4cfg = { diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 57f3a3ba0f..54d8b0dd5c 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 07a5fde7a1..1553a3af54 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A + select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 07a5464068..64776feee1 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -10,13 +10,15 @@ FLASH@0xfe000000 0x2000000 { RW_LEGACY(CBFS)@0x0 0xb00000 RW_SECTION_A@0xb00000 0x5e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x5cffc0 - RW_FWID_A@0x5dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x32ffc0 + RW_FWID_A@0x33ffc0 0x40 + ME_RW_A(CBFS)@0x340000 0x2a0000 } RW_SECTION_B@0x10e0000 0x5e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x5cffc0 - RW_FWID_B@0x5dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x32ffc0 + RW_FWID_B@0x33ffc0 0x40 + ME_RW_B(CBFS)@0x340000 0x2a0000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 0538e7403e..50e8f93080 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -66,6 +66,10 @@ static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_R7, NONE), }; +static const struct pad_config sd_gl9755s_pads[] = { + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + static void fw_config_handle(void *unused) { if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { @@ -81,7 +85,8 @@ static void fw_config_handle(void *unused) gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); @@ -93,5 +98,9 @@ static void fw_config_handle(void *unused) gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { + printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); + gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 0850e745db..ea9e08f294 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -136,6 +138,25 @@ static void mainboard_chip_init(void *chip_info) override_pads = variant_override_gpio_table(&override_num); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + /* + * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set + * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure + * the attached device is not mis-detected on resume from S0ix. + */ + if (gpio_get(GPP_A12)) { + const struct pad_config gpio_pedet_nvme[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1), + }; + gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme)); + printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n"); + } else { + const struct pad_config gpio_pedet_sata[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0), + }; + gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata)); + printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n"); + } } void mainboard_silicon_init_params(FSP_S_CONFIG *params) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 20a3843439..1590415d96 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -15,6 +15,7 @@ fw_config option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 + option MAX98360_ALC5682I_I2S 5 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 @@ -37,6 +38,10 @@ fw_config option SD_GL9755S 1 option SD_RTS5261 2 end + field KB_LAYOUT 20 21 + option KB_LAYOUT_DEFAULT 0 + option KB_LAYOUT_1 1 + end end chip soc/intel/tigerlake @@ -413,7 +418,10 @@ chip soc/intel/tigerlake device generic 0 on end end end # DPTF 0x9A03 - device ref tbt_pcie_rp0 on + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 end @@ -444,7 +452,26 @@ chip soc/intel/tigerlake device ref sata on end device ref pcie_rp1 on end device ref pcie_rp7 on end - device ref pcie_rp8 on end + device ref pcie_rp8 on + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD SD_GL9755S + end + end + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + register "is_external" = "1" + device generic 1 on + probe DB_SD SD_RTS5261 + end + end + end device ref pcie_rp9 on end device ref pcie_rp11 on end device ref uart0 on end diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3a2c..bebf38f788 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ static const struct pad_config override_gpio_table[] = { /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 5b9caa060e..bd4bf8041e 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -148,6 +148,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 3d627e3b81..24f80a05b8 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -80,7 +80,7 @@ static const struct pad_config override_gpio_table[] = { /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index f9ab7c95d3..72571c039a 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -123,7 +123,7 @@ chip soc/intel/tigerlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "30" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/volteer/variants/elemi/gpio.c b/src/mainboard/google/volteer/variants/elemi/gpio.c index 6868aca0eb..b86202b37f 100644 --- a/src/mainboard/google/volteer/variants/elemi/gpio.c +++ b/src/mainboard/google/volteer/variants/elemi/gpio.c @@ -26,7 +26,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B4 : CPU_GP3==> EN_PP3300_EMMC */ @@ -48,8 +48,6 @@ static const struct pad_config override_gpio_table[] = { /* C0 : SMBCLK ==> EN_PP3300_WLAN */ PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBCLK ==> EMMC_CLKREQ_ODL*/ - PAD_CFG_GPO(GPP_C1, 1, DEEP), /* C2 : SMBALERT# ==> GPP_C2_STRAP */ PAD_NC(GPP_C2, DN_20K), /* C3 : EMMC_PE_WAKE_ODL*/ @@ -78,7 +76,6 @@ static const struct pad_config override_gpio_table[] = { /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MOSI_STRAP */ @@ -139,10 +136,10 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_H2, DN_20K), /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H3, 1, DEEP), - /* H10 : SRCCLKREQ4# */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> WLAN_PERST_L*/ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> EMMC_CLKREQ_ODL*/ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* H16 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ @@ -185,6 +182,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B4 : CPU_GP3==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), @@ -207,8 +209,8 @@ static const struct pad_config early_gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), - /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ - PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H10 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 4afc795afd..d4c40f9795 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -6,6 +6,13 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Enable EMMC PCIE 5 using clk 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -184,6 +191,7 @@ chip soc/intel/tigerlake device generic 0 on end end end + device ref pcie_rp5 on end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index c3b5df7703..2a5b98d891 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -120,9 +120,8 @@ chip soc/intel/tigerlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -180,6 +179,19 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 2c95b1635b..6956848790 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -122,9 +122,8 @@ chip soc/intel/tigerlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc index 3c8ea4876f..7b69aa4504 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -2,5 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E -SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E, H9HCNNNFBMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53D1G64D4NW-046 WT:A diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt index 02e7443467..840f71a47a 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -1,3 +1,6 @@ DRAM Part Name ID to assign MT53E512M64D4NW-046 WT:E 0 (0000) MT53E1G64D8NW-046 WT:E 1 (0001) +H9HCNNNCRMBLPR-NEE 0 (0000) +H9HCNNNFBMBLPR-NEE 1 (0001) +MT53D1G64D4NW-046 WT:A 2 (0010) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index b74da4a5f0..c74fe433ba 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,2 +1,5 @@ MT53E512M64D4NW-046 WT:E MT53E1G64D8NW-046 WT:E +H9HCNNNCRMBLPR-NEE +H9HCNNNFBMBLPR-NEE +MT53D1G64D4NW-046 WT:A diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 069b2f0a98..5c10ec508e 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -29,6 +29,8 @@ static const struct pad_config override_gpio_table[] = { /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B3 : CPU_GP2 ==> PEN_DET_ODL */ PAD_CFG_GPI(GPP_B3, NONE, DEEP), /* B5 : ISH_I2C0_CVF_SDA */ diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index e4da0e6252..a1012a665a 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -36,6 +36,12 @@ chip soc/intel/tigerlake }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, }, .i2c[3] = { .speed = I2C_SPEED_FAST, @@ -275,6 +281,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d2b1354722..dd29553e82 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -194,6 +194,19 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 02181fba13..a0606cc59a 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -105,6 +105,7 @@ config ONBOARD_VGA_IS_PRIMARY config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH + select VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_VBNV_OFFSET hex @@ -129,7 +130,7 @@ config DRIVER_TPM_I2C_ADDR config PICASSO_FW_A_POSITION hex default 0xFF012040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_A region. This is the start of the RW-A region + 64 bytes for the cbfs header. @@ -137,7 +138,7 @@ config PICASSO_FW_A_POSITION config PICASSO_FW_B_POSITION hex default 0xFF312040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_B region. This is the start of the RW-A region + 64 bytes for the cbfs header. @@ -225,21 +226,21 @@ config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW Minimum board version where the variant starts supporting active low power enable for WiFi. -config VBOOT_STARTS_BEFORE_BOOTBLOCK - bool "PSP verstage" - default y if VBOOT +config VARIANT_HAS_FPMCU + bool + default y if BOARD_GOOGLE_BERKNIP + default y if BOARD_GOOGLE_MORPHIUS + default n help - Firmware verification happens before the main processor is brought - online. + Select y if any SKU of the board has a fingerprint sensor -config VBOOT_STARTS_IN_BOOTBLOCK - bool "X86 verstage (in bootblock)" - depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE +config VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER + int + default 4 if BOARD_GOOGLE_MORPHIUS + default 3 if BOARD_GOOGLE_BERKNIP + default 0 help - Firmware verification happens during the end of or right after the - bootblock. This implies that a static VBOOT2_WORK() buffer must be - allocated in memlayout. + Last board version that needs the extra delay for FPMCU init. config EFS_SPI_READ_MODE int @@ -263,5 +264,6 @@ config CHROMEOS_WIFI_SAR select SAR_ENABLE select USE_SAR select GEO_SAR_ENABLE + select HAVE_REGULATORY_DOMAIN if BOARD_GOOGLE_VILBOZ endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 88aef867de..96c97b68d3 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -9,11 +9,7 @@ ramstage-y += chromeos.c ramstage-y += ec.c ramstage-y += sku_id.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-y += verstage.c -else -verstage-y += chromeos.c -endif smm-y += smihandler.c diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index a7636de702..87e028573c 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -2,16 +2,15 @@ #include #include +#include void bootblock_mainboard_early_init(void) { size_t num_gpios; const struct soc_amd_gpio *gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - program_gpios(gpios, num_gpios); - } + gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); + program_gpios(gpios, num_gpios); variant_pcie_gpio_configure(); } diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 9503d3762c..6d930d0e7a 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -247,12 +247,13 @@ static void mainboard_final(void *chip_info) gnvs = acpi_get_gnvs(); - if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } + + finalize_gpios(acpi_get_sleep_type()); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index c8d57ff9b5..2764a89b08 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -7,10 +7,8 @@ bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c verstage-y += gpio_baseboard_common.c verstage-y += helpers.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -endif verstage-y += tpm_tis.c romstage-y += gpio_baseboard_common.c diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 2398d07d74..884862d3dd 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,7 +30,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ + /* S0iX SLP - (unused - goes to EC */ PAD_NC(GPIO_10), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), @@ -97,8 +97,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPI(GPIO_84, PULL_NONE), /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ PAD_GPO(GPIO_85, HIGH), - /* RAM ID 2 */ - PAD_GPI(GPIO_86, PULL_NONE), + /* RAM ID 2 - Keep High */ + PAD_GPO(GPIO_86, HIGH), /* EMMC_DATA7 */ PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), /* EMMC_DATA5 */ @@ -291,6 +291,16 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ +} + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + *size = 0; + return NULL; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a436d1c3d0..14b85b0da9 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include +#include #include #include #include @@ -32,8 +34,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_NC(GPIO_10), - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -71,8 +71,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -87,7 +85,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic /* EMMC_RESET_L */ PAD_GPO(GPIO_68, HIGH), - /* FPMCU_BOOT0 - TODO: Check this */ + /* FPMCU_BOOT0 */ PAD_GPO(GPIO_69, LOW), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), @@ -300,6 +298,51 @@ __weak void variant_pcie_gpio_configure(void) wifi_power_reset_configure_pre_v3(); } +__weak void finalize_gpios(int slp_typ) +{ + if (variant_has_fingerprint() && slp_typ != ACPI_S3) { + + if (fpmcu_needs_delay()) + mdelay(550); + + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + +static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + if (variant_has_fingerprint()) { + if (slp_typ == ACPI_S3) + return NULL; + + *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); + return gpio_fingerprint_bootblock_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); + return gpio_no_fingerprint_bootblock_table; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), @@ -307,8 +350,25 @@ static const struct soc_amd_gpio gpio_sleep_table[] = { PAD_GPO(GPIO_76, LOW), }; +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), + + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) { + if (slp_typ == SLP_TYP_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 70710351d2..d12a8ed407 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -149,3 +149,31 @@ int variant_get_daughterboard_id(void) { return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); } + +bool variant_has_fingerprint(void) +{ + if (CONFIG(VARIANT_HAS_FPMCU)) + return true; + + return false; +} + +bool fpmcu_needs_delay(void) +{ + /* + * Older board versions need an extra delay here to finish resetting + * the FPMCU. The resistor value in the glitch prevention circuit was + * sized so that the FPMCU doesn't turn of for ~1 second. On newer + * boards, that's been updated to ~30ms, which allows the FPMCU's + * reset to be completed in the time between bootblock and finalize. + */ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER) + return true; + + return false; +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 338b918623..4ec6addfe7 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -24,12 +24,17 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); */ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); +/* This function provides GPIO init in bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ); + /* * This function provides GPIO table for the pads that need to be configured when entering * sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* Program any required GPIOs at the finalize phase */ +void finalize_gpios(int slp_typ); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ @@ -69,9 +74,13 @@ bool variant_uses_v3_schematics(void); bool variant_uses_v3_6_schematics(void); /* Return true if variant uses CODEC_GPI pin for headphone jack interrupt. */ bool variant_uses_codec_gpi(void); -/* Return true if variant has active low power enable fow WiFi. */ +/* Return true if variant has active low power enable for WiFi. */ bool variant_has_active_low_wifi_power(void); /* Return value of daughterboard ID */ int variant_get_daughterboard_id(void); +/* Return true if the board has a fingerprint sensor. */ +bool variant_has_fingerprint(void); +/* Return true if the board needs an extra fpmcu delay. */ +bool fpmcu_needs_delay(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index d2dd104e89..f86d926e2e 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -37,8 +37,6 @@ static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* EN_PWR_WIFI */ @@ -62,8 +60,6 @@ static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* FPMCU_BOOT0 Change NC */ PAD_NC(GPIO_69), /* EN_DEV_BEEP_L */ diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index cb98df7d41..329e7dddb3 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -10,10 +10,6 @@ static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ @@ -37,10 +33,6 @@ static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 039a437a1a..a44d4ac43d 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -277,9 +277,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), - /* HPD_1 (A19) and HPD_2 (A20) pins */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* IMGCLKOUT */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 05f45922e2..57be7f19e9 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -7,13 +7,15 @@ FLASH@0xff000000 0x1000000 { SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x12ffc0 + RW_FWID_A@0x13ffc0 0x40 + ME_RW_A(CBFS)@0x140000 0x190000 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x12ffc0 + RW_FWID_B@0x13ffc0 0x40 + ME_RW_B(CBFS)@0x140000 0x190000 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 46499f48f1..bea9cd80d4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h new file mode 100644 index 0000000000..b89ad5a8db --- /dev/null +++ b/src/mainboard/scaleway/tagada/gpio_defs.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_GPIO_DEFS_H +#define _MAINBOARD_GPIO_DEFS_H + +#include + +// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED +#define GPIO_GPIO_0 0 +#define R_PAD_CFG_DW0_GPIO_0 0x4d8 +#define PID_GPIO_0 PID_NorthCommunity + +// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn +#define GPIO_GPIO_4 4 +#define R_PAD_CFG_DW0_GPIO_4 0x568 +#define PID_GPIO_4 PID_SouthCommunity + +// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn +#define GPIO_GPIO_5 5 +#define R_PAD_CFG_DW0_GPIO_5 0x570 +#define PID_GPIO_5 PID_SouthCommunity + + +// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select +#define GPIO_GPIO_8 8 +#define R_PAD_CFG_DW0_GPIO_8 0x5c8 +#define PID_GPIO_8 PID_SouthCommunity + +// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose +#define GPIO_GPIO_9 9 +#define R_PAD_CFG_DW0_GPIO_9 0x5d0 +#define PID_GPIO_9 PID_SouthCommunity + +#endif /* _MAINBOARD_GPIO_DEFS_H */ diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index fd6afa8637..78599230d7 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -1,12 +1,62 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +#include #include +#ifdef __RAMSTAGE__ +static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config) +{ + uint32_t reg32; + bool m2a_pcie, m2b_pcie; + uint8_t entry; + + /* Detects modules type */ + // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4, R_PAD_CFG_DW0_GPIO_4)); + m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; + // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5, R_PAD_CFG_DW0_GPIO_5)); + m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; + + printk(BIOS_DEBUG, + "GPIO values from M2 slots A:%d B:%d " + "(0=SATA, 1=PCIe or not populated)\n", + m2a_pcie, m2b_pcie); + + // HSIO default config is for PCIe, only update for SATA + // (also secondary PCIe lines are already set depending on SKU) + for (entry = 0; entry < num_of_entry; entry++) { + BL_ME_FIA_MUX_CONFIG *mux_config = &(config[entry].FiaConfig.MuxConfiguration); + BL_ME_FIA_SATA_CONFIG *sata_config = + &(config[entry].FiaConfig.SataLaneConfiguration); + if (!m2a_pcie) { + // change Lane 14 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + if (!m2b_pcie) { + // change Lane 12 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + } +} +#endif + size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { - size_t num; - num = ARRAY_SIZE(tagada_hsio_config); - (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; - return num; + size_t num; + num = ARRAY_SIZE(tagada_hsio_config); +#ifdef __RAMSTAGE__ + update_hsio_info_for_m2_slots(num, tagada_hsio_config); +#endif + (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; + return num; } diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index 4e3a2c11b2..8a25a04011 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -6,7 +6,7 @@ #include #ifndef __ACPI__ -const BL_HSIO_INFORMATION tagada_hsio_config[] = { +DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = { /* * Supported Lanes: * 20 diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c index fd1c715eb2..67636575ce 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/romstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c @@ -6,8 +6,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, }, diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a5b2e5efb6..63806819de 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,7 @@ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c +romstage-y += raminit_iosav.c romstage-y += raminit_native.c romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e520..b67eb564ca 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -18,31 +19,6 @@ /* FIXME: no support for 3-channel chipsets */ -/* Number of programmed IOSAV subsequences. */ -static unsigned int ssq_count = 0; - -static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) -{ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; - - ssq_count++; -} - -static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) -{ - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); - - ssq_count = 0; -} - -static void iosav_run_once(const int ch) -{ - iosav_run_queue(ch, 1, 0); -} - static void sfence(void) { asm volatile ("sfence"); @@ -52,9 +28,9 @@ static void sfence(void) static void toggle_io_reset(void) { u32 r32 = MCHBAR32(MC_INIT_STATE_G); - MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); udelay(1); - MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); udelay(1); } @@ -80,41 +56,6 @@ static u32 get_XOVER_CMD(u8 rankmap) return reg; } -/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ -u8 get_CWL(u32 tCK) -{ - /* Get CWL based on tCK using the following rule */ - switch (tCK) { - case TCK_1333MHZ: - return 12; - - case TCK_1200MHZ: - case TCK_1100MHZ: - return 11; - - case TCK_1066MHZ: - case TCK_1000MHZ: - return 10; - - case TCK_933MHZ: - case TCK_900MHZ: - return 9; - - case TCK_800MHZ: - case TCK_700MHZ: - return 8; - - case TCK_666MHZ: - return 7; - - case TCK_533MHZ: - return 6; - - default: - return 5; - } -} - void dram_find_common_params(ramctr_timing *ctrl) { size_t valid_dimms; @@ -190,11 +131,11 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -271,7 +212,7 @@ void dram_timing_regs(ramctr_timing *ctrl) printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + MCHBAR32_OR(TC_RFP_ch(channel), 0xff); /* Self-refresh timing parameters */ reg = 0; @@ -581,14 +522,6 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) } } -static void wait_for_iosav(int channel) -{ - while (1) { - if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) - return; - } -} - static void write_reset(ramctr_timing *ctrl) { int channel, slotrank; @@ -601,27 +534,7 @@ static void write_reset(ramctr_timing *ctrl) /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); /* * Execute command queue - why is bit 22 set here?! @@ -652,19 +565,19 @@ void dram_jedecreset(ramctr_timing *ctrl) MCHBAR32(MC_INIT_STATE_G) = reg; /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); /* XXX Wait 20ns */ udelay(1); @@ -685,33 +598,26 @@ void dram_jedecreset(ramctr_timing *ctrl) } } -static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) +/* + * DDR3 Rank1 Address mirror swap the following pins: + * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 + */ +static void ddr3_mirror_mrreg(int *bank, u32 *addr) { - /* Get ODT based on rankmap */ - int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); - - if (dimms_per_ch == 1) { - return (const odtmap){60, 60}; - } else { - return (const odtmap){120, 30}; - } + *bank = ((*bank >> 1) & 1) | ((*bank << 1) & 2); + *addr = (*addr & ~0x1f8) | ((*addr >> 1) & 0xa8) | ((*addr & 0xa8) << 1); } static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) { wait_for_iosav(channel); - if (ctrl->rank_mirror[channel][slotrank]) { - /* DDR3 Rank1 Address mirror - swap the following pins: - A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ - reg = ((reg >> 1) & 1) | ((reg << 1) & 2); - val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); - } + if (ctrl->rank_mirror[channel][slotrank]) + ddr3_mirror_mrreg(®, &val); - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command MRS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, }, @@ -727,13 +633,9 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command MRS */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -750,15 +652,11 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command MRS */ + [2] = { .sp_cmd_ctrl = { - .command = IOSAV_MRS, + .command = IOSAV_MRS, }, .subseq_ctrl = { .cmd_executions = 1, @@ -772,9 +670,9 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -786,9 +684,6 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; - /* DLL Reset - self clearing - set after CLK frequency has been changed */ - mr0reg = 0x100; - /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { mch_cas = (u16) ((ctrl->CAS - 4) << 1); @@ -800,12 +695,15 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) /* Convert tWR to MCH register friendly */ mch_wr = mch_wr_t[ctrl->tWR - 5]; - mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); - mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); - mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); + /* DLL Reset - self clearing - set after CLK frequency has been changed */ + mr0reg = 1 << 8; + + mr0reg |= (mch_cas & 0x1) << 2; + mr0reg |= (mch_cas & 0xe) << 3; + mr0reg |= mch_wr << 9; /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); + mr0reg |= !is_mobile << 12; return mr0reg; } @@ -814,6 +712,18 @@ static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); } +static odtmap get_ODT(ramctr_timing *ctrl, int channel) +{ + /* Get ODT based on rankmap */ + int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); + + if (dimms_per_ch == 1) { + return (const odtmap){60, 60}; + } else { + return (const odtmap){120, 30}; + } +} + static u32 encode_odt(u32 odt) { switch (odt) { @@ -834,7 +744,7 @@ static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) odtmap odt; u32 mr1reg; - odt = get_ODT(ctrl, rank, channel); + odt = get_ODT(ctrl, channel); mr1reg = 2; mr1reg |= encode_odt(odt.rttnom); @@ -853,24 +763,38 @@ static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) { - u16 pasr, cwl, mr2reg; - odtmap odt; - int srt; + const u16 pasr = 0; + const u16 cwl = ctrl->CWL - 5; + const odtmap odt = get_ODT(ctrl, channel); - pasr = 0; - cwl = ctrl->CWL - 5; - odt = get_ODT(ctrl, rank, channel); + int srt = 0; + if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) + srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; - srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; - - mr2reg = 0; - mr2reg = (mr2reg & ~0x07) | pasr; - mr2reg = (mr2reg & ~0x38) | (cwl << 3); - mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); - mr2reg = (mr2reg & ~0x80) | (srt << 7); + u16 mr2reg = 0; + mr2reg |= pasr; + mr2reg |= cwl << 3; + mr2reg |= ctrl->auto_self_refresh << 6; + mr2reg |= srt << 7; mr2reg |= (odt.rttwr / 60) << 9; write_mrreg(ctrl, channel, rank, 2, mr2reg); + + /* Program MR2 shadow */ + u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); + + reg32 &= 3 << 14 | 3 << 6; + + reg32 |= mr2reg & ~(3 << 6); + + if (rank & 1) { + if (srt) + reg32 |= 1 << (rank / 2 + 6); + } else { + if (ctrl->rank_mirror[channel][rank]) + reg32 |= 1 << (rank / 2 + 14); + } + MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; } static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) @@ -899,11 +823,11 @@ void dram_mrscommands(ramctr_timing *ctrl) } } - /* DRAM command NOP (without ODT nor chip selects) */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq zqcl_sequence[] = { + /* DRAM command NOP (without ODT nor chip selects) */ + [0] = { .sp_cmd_ctrl = { - .command = IOSAV_NOP & ~(0xff << 8), + .command = IOSAV_NOP & ~(0xff << 8), }, .subseq_ctrl = { .cmd_executions = 1, @@ -917,13 +841,9 @@ void dram_mrscommands(ramctr_timing *ctrl) .bank = 0, .rank = 0, }, - }; - iosav_write_ssq(BROADCAST_CH, &ssq); - } - - /* DRAM command ZQCL */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ZQCL */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, .ranksel_ap = 1, @@ -941,12 +861,12 @@ void dram_mrscommands(ramctr_timing *ctrl) .rank = 0, }, .addr_update = { - .inc_rank = 1, - .addr_wrap = 20, + .inc_rank = 1, + .addr_wrap = 20, }, - }; - iosav_write_ssq(BROADCAST_CH, &ssq); - } + }, + }; + iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); /* Execute command queue on all channels. Do it four times. */ iosav_run_queue(BROADCAST_CH, 4, 0); @@ -957,10 +877,10 @@ void dram_mrscommands(ramctr_timing *ctrl) } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); wait_for_iosav(channel); @@ -969,30 +889,7 @@ void dram_mrscommands(ramctr_timing *ctrl) /* Drain */ wait_for_iosav(channel); - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 101, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1072,7 +969,7 @@ void program_timings(ramctr_timing *ctrl, int channel) MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); - reg_io_latency &= 0xffff0000; + reg_io_latency &= ~0xffff; reg_roundtrip_latency = 0; @@ -1152,106 +1049,7 @@ static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 15, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 36, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); /* Execute command queue */ iosav_run_once(channel); @@ -1308,7 +1106,7 @@ static struct run get_longest_zero_run(int *seq, int sz) return ret; } -static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA; int statistics[NUM_LANES][128]; @@ -1338,7 +1136,7 @@ static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, } } -static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA_delta; int statistics[NUM_LANES][51]; @@ -1384,7 +1182,7 @@ static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, i } } -static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; int lane; @@ -1433,53 +1231,74 @@ static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *up return 0; } -struct timA_minmax { - int timA_min_high, timA_max_high; -}; - -static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, - struct timA_minmax *mnmx) +static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) { int lane; - mnmx->timA_min_high = 7; - mnmx->timA_max_high = 0; + u16 logic_delay_min = 7; + u16 logic_delay_max = 0; FOR_ALL_LANES { - if (mnmx->timA_min_high > - (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) - mnmx->timA_min_high = - (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); - if (mnmx->timA_max_high < - (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) - mnmx->timA_max_high = - (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); + const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + + logic_delay_min = MIN(logic_delay_min, logic_delay); + logic_delay_max = MAX(logic_delay_max, logic_delay); } + + if (logic_delay_max < logic_delay_min) { + printk(BIOS_EMERG, "Logic delay max < min (%u < %u): %d, %d\n", + logic_delay_max, logic_delay_min, channel, slotrank); + } + + assert(logic_delay_max >= logic_delay_min); + + return logic_delay_max - logic_delay_min; } -static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, - struct timA_minmax *mnmx) +static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int slotrank, int prev) { - struct timA_minmax post; - int shift_402x = 0; + int latency_offset = 0; /* Get changed maxima */ - pre_timA_change(ctrl, channel, slotrank, &post); + const int post = get_logic_delay_delta(ctrl, channel, slotrank); - if (mnmx->timA_max_high - mnmx->timA_min_high < - post.timA_max_high - post.timA_min_high) - shift_402x = +1; + if (prev < post) + latency_offset = +1; - else if (mnmx->timA_max_high - mnmx->timA_min_high > - post.timA_max_high - post.timA_min_high) - shift_402x = -1; + else if (prev > post) + latency_offset = -1; else - shift_402x = 0; + latency_offset = 0; - ctrl->timings[channel][slotrank].io_latency += shift_402x; - ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; - printram("4024 += %d;\n", shift_402x); - printram("4028 += %d;\n", shift_402x); + ctrl->timings[channel][slotrank].io_latency += latency_offset; + ctrl->timings[channel][slotrank].roundtrip_latency += latency_offset; + printram("4024 += %d;\n", latency_offset); + printram("4028 += %d;\n", latency_offset); + + return post; +} + +static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slotrank) +{ + u16 logic_delay_min = 7; + int lane; + + FOR_ALL_LANES { + const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + + logic_delay_min = MIN(logic_delay_min, logic_delay); + } + + if (logic_delay_min >= 2) { + printk(BIOS_WARNING, "Logic delay %u greater than 1: %d %d\n", + logic_delay_min, channel, slotrank); + } + + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timA -= logic_delay_min << 6; + } + ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; + printram("4028 -= %d;\n", logic_delay_min); } /* @@ -1508,32 +1327,11 @@ int read_training(ramctr_timing *ctrl) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int all_high, some_high; int upperA[NUM_LANES]; - struct timA_minmax mnmx; + int prev; wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); /* Execute command queue */ iosav_run_once(channel); @@ -1544,7 +1342,7 @@ int read_training(ramctr_timing *ctrl) ctrl->timings[channel][slotrank].roundtrip_latency = 55; program_timings(ctrl, channel); - discover_timA_coarse(ctrl, channel, slotrank, upperA); + find_rcven_pi_coarse(ctrl, channel, slotrank, upperA); all_high = 1; some_high = 0; @@ -1572,28 +1370,21 @@ int read_training(ramctr_timing *ctrl) program_timings(ctrl, channel); - pre_timA_change(ctrl, channel, slotrank, &mnmx); + prev = get_logic_delay_delta(ctrl, channel, slotrank); - err = discover_402x(ctrl, channel, slotrank, upperA); + err = find_roundtrip_latency(ctrl, channel, slotrank, upperA); if (err) return err; - post_timA_change(ctrl, channel, slotrank, &mnmx); - pre_timA_change(ctrl, channel, slotrank, &mnmx); + prev = align_rt_io_latency(ctrl, channel, slotrank, prev); - discover_timA_fine(ctrl, channel, slotrank, upperA); + fine_tune_rcven_pi(ctrl, channel, slotrank, upperA); - post_timA_change(ctrl, channel, slotrank, &mnmx); - pre_timA_change(ctrl, channel, slotrank, &mnmx); + prev = align_rt_io_latency(ctrl, channel, slotrank, prev); - FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= - mnmx.timA_min_high * 0x40; - } - ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; - printram("4028 -= %d;\n", mnmx.timA_min_high); + compute_final_logic_delay(ctrl, channel, slotrank); - post_timA_change(ctrl, channel, slotrank, &mnmx); + align_rt_io_latency(ctrl, channel, slotrank, prev); printram("4/8: %d, %d, %x, %x\n", channel, slotrank, ctrl->timings[channel][slotrank].roundtrip_latency, @@ -1612,13 +1403,13 @@ int read_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; } -static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) +static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) { int lane; @@ -1629,120 +1420,17 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 500, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_misc_write_sequence(ctrl, channel, slotrank, + MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq rd_sequence[] = { + /* DRAM command PREA */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1762,13 +1450,9 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ACT */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -1789,13 +1473,9 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -1816,13 +1496,9 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PREA */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1840,11 +1516,11 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) .rank = slotrank, }, .addr_update = { - .addr_wrap = 18, + .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1852,7 +1528,7 @@ static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); } -static void timC_threshold_process(int *data, const int count) +static void tx_dq_threshold_process(int *data, const int count) { int min = data[0]; int max = min; @@ -1871,51 +1547,27 @@ static void timC_threshold_process(int *data, const int count) printram("threshold=%d min=%d max=%d\n", threshold, min, max); } -static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) +static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) { - int timC; + int tx_dq; int stats[NUM_LANES][MAX_TIMC + 1]; int lane; wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); /* Execute command queue */ iosav_run_once(channel); - for (timC = 0; timC <= MAX_TIMC; timC++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { + FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = tx_dq; program_timings(ctrl, channel); - test_timC(ctrl, channel, slotrank); + test_tx_dq(ctrl, channel, slotrank); FOR_ALL_LANES { - stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { @@ -1928,7 +1580,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) * With command training not being done yet, the lane can be erroneous. * Take the average as reference and try again to find a run. */ - timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); + tx_dq_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); if (rn.all || rn.length < 8) { @@ -1953,6 +1605,12 @@ static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) return ret; } +/* Each cacheline is 64 bits long */ +static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) +{ + MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; +} + static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) { unsigned int j; @@ -1962,6 +1620,8 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); + + program_wdb_pattern_length(channel, 8); } static int num_of_channels(const ramctr_timing *ctrl) @@ -1985,6 +1645,8 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel) write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); sfence(); + + program_wdb_pattern_length(channel, 16); } static void precharge(ramctr_timing *ctrl) @@ -2002,107 +1664,8 @@ static void precharge(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2120,107 +1683,8 @@ static void precharge(ramctr_timing *ctrl) FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2233,12 +1697,13 @@ static void precharge(ramctr_timing *ctrl) static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { /* enable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7); wait_for_iosav(channel); - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + + const struct iosav_ssq sequence[] = { + /* DRAM command NOP */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -2255,13 +1720,9 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_NOP_ALT, .ranksel_ap = 1, @@ -2278,9 +1739,9 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2288,7 +1749,8 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); /* disable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, + make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); } static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) @@ -2346,17 +1808,17 @@ static int get_timB_high_adjust(u64 val) { int i; - /* good */ + /* DQS is good enough */ if (val == 0xffffffffffffffffLL) return 0; if (val >= 0xf000000000000000LL) { - /* needs negative adjustment */ + /* DQS is late, needs negative adjustment */ for (i = 0; i < 8; i++) if (val << (8 * (7 - i) + 4)) return -i; } else { - /* needs positive adjustment */ + /* DQS is early, needs positive adjustment */ for (i = 0; i < 8; i++) if (val >> (8 * (7 - i) + 4)) return i; @@ -2364,130 +1826,30 @@ static int get_timB_high_adjust(u64 val) return 8; } -static void adjust_high_timB(ramctr_timing *ctrl) +static void train_write_flyby(ramctr_timing *ctrl) { int channel, slotrank, lane, old; MCHBAR32(GDCRTRAININGMOD) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { + /* Reset read and write WDB pointers */ MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 4, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq rd_sequence[] = { + /* DRAM command PREA */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -2507,13 +1869,9 @@ static void adjust_high_timB(ramctr_timing *ctrl) .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ACT */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -2530,13 +1888,9 @@ static void adjust_high_timB(ramctr_timing *ctrl) .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 3, @@ -2555,9 +1909,9 @@ static void adjust_high_timB(ramctr_timing *ctrl) .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2588,30 +1942,7 @@ static void write_op(ramctr_timing *ctrl, int channel) /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -2637,15 +1968,15 @@ int write_training(ramctr_timing *ctrl) int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2655,7 +1986,7 @@ int write_training(ramctr_timing *ctrl) Only NOP is allowed in this mode */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 0x1080); + make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); MCHBAR32(GDCRTRAININGMOD) = 0x108052; @@ -2678,37 +2009,14 @@ int write_training(ramctr_timing *ctrl) wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 101, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = 0, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -2722,17 +2030,16 @@ int write_training(ramctr_timing *ctrl) precharge(ctrl); printram("CPF\n"); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timC(ctrl, channel, slotrank); + err = tx_dq_write_leveling(ctrl, channel, slotrank); if (err) return err; } @@ -2741,18 +2048,18 @@ int write_training(ramctr_timing *ctrl) program_timings(ctrl, channel); /* measure and adjust timB timings */ - adjust_high_timB(ctrl); + train_write_flyby(ctrl); FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; } -static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) +static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) { struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; int timC_delta; @@ -2770,125 +2077,17 @@ static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; } + /* Reset read WDB pointer */ MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 8, - .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = ctr, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - .lfsr_upd = 3, - .lfsr_xors = 2, - }, - }; - iosav_write_ssq(channel, &ssq); - } - /* FIXME: Hardcoded subsequence index */ + iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); + + /* Program LFSR for the RD/WR subsequences */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - .lfsr_upd = 3, - .lfsr_xors = 2, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* FIXME: Hardcoded subsequence index */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 15, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - /* Execute command queue */ iosav_run_once(channel); @@ -2937,6 +2136,8 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) } sfence(); } + + program_wdb_pattern_length(channel, 256); } static void reprogram_320c(ramctr_timing *ctrl) @@ -2949,70 +2150,24 @@ static void reprogram_320c(ramctr_timing *ctrl) /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -3029,14 +2184,18 @@ static void reprogram_320c(ramctr_timing *ctrl) toggle_io_reset(); } +#define CT_MIN_PI -127 +#define CT_MAX_PI 128 +#define CT_PI_LENGTH (CT_MAX_PI - CT_MIN_PI + 1) + #define MIN_C320C_LEN 13 static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) { struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; int slotrank; - int c320c; - int stat[NUM_SLOTRANKS][256]; + int command_pi; + int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; int delta = 0; printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); @@ -3065,20 +2224,21 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) ctrl->timings[channel][slotrank].roundtrip_latency -= delta; } - for (c320c = -127; c320c <= 127; c320c++) { + for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank].pi_coding = c320c; + ctrl->timings[channel][slotrank].pi_coding = command_pi; } program_timings(ctrl, channel); reprogram_320c(ctrl); FOR_ALL_POPULATED_RANKS { - stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); + stat[slotrank][command_pi - CT_MIN_PI] = + test_command_training(ctrl, channel, slotrank); } } FOR_ALL_POPULATED_RANKS { - struct run rn = get_longest_zero_run(stat[slotrank], 255); + struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); - ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; + ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, rn.start, rn.middle, rn.end); @@ -3104,7 +2264,6 @@ int command_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -3143,13 +2302,13 @@ int command_training(ramctr_timing *ctrl) } FOR_ALL_POPULATED_CHANNELS - program_timings(ctrl, channel); + program_timings(ctrl, channel); reprogram_320c(ctrl); return 0; } -static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; @@ -3169,107 +2328,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 500, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -3295,7 +2355,64 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, i return 0; } -int discover_edges(ramctr_timing *ctrl) +static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) +{ + int slotrank, lane; + + fill_pattern0(ctrl, channel, 0, 0); + FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + } + + FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].falling = 16; + ctrl->timings[channel][slotrank].lanes[lane].rising = 16; + } + + program_timings(ctrl, channel); + + FOR_ALL_POPULATED_RANKS { + wait_for_iosav(channel); + + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + + /* Execute command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } + + /* XXX: check any measured value ? */ + + FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].falling = 48; + ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + } + + program_timings(ctrl, channel); + + FOR_ALL_POPULATED_RANKS { + wait_for_iosav(channel); + + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + + /* Execute command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } + + /* XXX: check any measured value ? */ + + FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = + ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; + } +} + +int read_mpr_training(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -3306,264 +2423,14 @@ int discover_edges(ramctr_timing *ctrl) toggle_io_reset(); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - FOR_ALL_POPULATED_CHANNELS { - fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - - /* XXX: check any measured value ? */ - - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - - /* XXX: check any measured value ? */ - - FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = - ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; - } + find_predefined_pattern(ctrl, channel); fill_pattern0(ctrl, channel, 0, 0xffffffff); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } /* @@ -3574,7 +2441,7 @@ int discover_edges(ramctr_timing *ctrl) printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_real(ctrl, channel, slotrank, + err = find_read_mpr_margin(ctrl, channel, slotrank, falling_edges[channel][slotrank]); if (err) return err; @@ -3584,7 +2451,7 @@ int discover_edges(ramctr_timing *ctrl) printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_real(ctrl, channel, slotrank, + err = find_read_mpr_margin(ctrl, channel, slotrank, rising_edges[channel][slotrank]); if (err) return err; @@ -3603,7 +2470,7 @@ int discover_edges(ramctr_timing *ctrl) program_timings(ctrl, channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -3631,7 +2498,6 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { @@ -3649,110 +2515,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = MAX(ctrl->tRRD, - (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 20, - .post_ssq_wait = ctrl->tWTR + - ctrl->CWL + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 20, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_data_write_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); @@ -3792,7 +2555,8 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } } - MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; + /* Restore nominal Vref after training */ + MCHBAR32(GDCRTRAININGMOD_ch(channel)) = 0; printram("CPA\n"); return 0; } @@ -3840,7 +2604,7 @@ int discover_edges_write(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -3850,109 +2614,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 480, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 480, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); @@ -4000,7 +2662,6 @@ int discover_timC_write(ramctr_timing *ctrl) stats[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES { @@ -4106,18 +2767,6 @@ void normalize_training(ramctr_timing *ctrl) } } -void write_controller_mr(ramctr_timing *ctrl) -{ - int channel, slotrank; - - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = - make_mr0(ctrl, slotrank); - MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = - make_mr1(ctrl, slotrank, channel); - } -} - int channel_test(ramctr_timing *ctrl) { int channel, slotrank, lane; @@ -4130,8 +2779,6 @@ int channel_test(ramctr_timing *ctrl) } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) @@ -4143,112 +2790,7 @@ int channel_test(ramctr_timing *ctrl) } wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = 8, - .post_ssq_wait = 40, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 100, - .cmd_delay_gap = 4, - .post_ssq_wait = 40, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 100, - .cmd_delay_gap = 4, - .post_ssq_wait = 40, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 40, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }; - iosav_write_ssq(channel, &ssq); - } + iosav_write_memory_test_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); @@ -4272,7 +2814,6 @@ void channel_scrub(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } /* @@ -4281,7 +2822,7 @@ void channel_scrub(ramctr_timing *ctrl) * The following loops writes to every DRAM address, setting the ECC bits to the * correct value. A read from this location will no longer return a CRC error, * except when a bit has toggled due to external events. - * The same could be accieved by writing to the physical memory map, but it's + * The same could be achieved by writing to the physical memory map, but it's * much more difficult due to SMM remapping, ME stolen memory, GFX stolen memory, * and firmware running in x86_32. */ @@ -4290,13 +2831,13 @@ void channel_scrub(ramctr_timing *ctrl) for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { - /* - * DRAM command ACT - * Opens the row for writing. - */ - { - u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); - const struct iosav_ssq ssq = { + u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); + const struct iosav_ssq sequence[] = { + /* + * DRAM command ACT + * Opens the row for writing. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -4317,17 +2858,13 @@ void channel_scrub(ramctr_timing *ctrl) .inc_addr_1 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command WR - * Writes (128 + 1) * 8 (burst length) * 8 (bus width) - * bytes. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command WR + * Writes (128 + 1) * 8 (burst length) * 8 (bus width) + * bytes. + */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -4349,16 +2886,12 @@ void channel_scrub(ramctr_timing *ctrl) .inc_addr_8 = 1, .addr_wrap = 9, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command PRE - * Closes the row. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command PRE + * Closes the row. + */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -4376,11 +2909,11 @@ void channel_scrub(ramctr_timing *ctrl) .rank = slotrank, }, .addr_update = { - .addr_wrap = 18, + .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_queue(channel, 16, 0); @@ -4401,7 +2934,7 @@ void set_scrambling_seed(ramctr_timing *ctrl) {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; + MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; @@ -4423,7 +2956,7 @@ void prepare_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); } udelay(1); @@ -4453,7 +2986,7 @@ void set_read_write_timings(ramctr_timing *ctrl) dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | + MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -4462,8 +2995,8 @@ void set_normal_operation(ramctr_timing *ctrl) { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; + MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); } } @@ -4476,7 +3009,7 @@ static int encode_wm(int ns) /* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { - const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; + const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; @@ -4487,7 +3020,7 @@ void final_registers(ramctr_timing *ctrl) MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4528,8 +3061,8 @@ void final_registers(ramctr_timing *ctrl) FOR_ALL_CHANNELS MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); - MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel */ @@ -4555,14 +3088,14 @@ void final_registers(ramctr_timing *ctrl) /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } void restore_timings(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, lane; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(TC_RAP_ch(channel)) = @@ -4581,16 +3114,16 @@ void restore_timings(ramctr_timing *ctrl) wait_for_iosav(channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } printram("CPE\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 32f2b44d4b..80693bb30e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,25 @@ struct iosav_ssq { } addr_update; }; +typedef struct ramctr_timing_st ramctr_timing; + +void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); +void iosav_run_once(const int ch); +void wait_for_iosav(int channel); + +void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); +void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); +void iosav_write_read_mpr_sequence( + int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); +void iosav_write_command_training_sequence( + ramctr_timing *ctrl, int channel, int slotrank, unsigned int address); +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank); +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank); + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 @@ -227,7 +246,6 @@ typedef struct ramctr_timing_st { #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) #define GET_ERR_CHANNEL(x) (x >> 16) -u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing *ctrl); void program_timings(ramctr_timing *ctrl, int channel); void dram_find_common_params(ramctr_timing *ctrl); @@ -241,11 +259,10 @@ void dram_jedecreset(ramctr_timing *ctrl); int read_training(ramctr_timing *ctrl); int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); -int discover_edges(ramctr_timing *ctrl); +int read_mpr_training(ramctr_timing *ctrl); int discover_edges_write(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); -void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); void set_wmm_behavior(const u32 cpu); diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c new file mode 100644 index 0000000000..11b2acb252 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -0,0 +1,689 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "raminit_native.h" +#include "raminit_common.h" +#include "raminit_tables.h" +#include "sandybridge.h" + +/* FIXME: no support for 3-channel chipsets */ + +/* Number of programmed IOSAV subsequences. */ +static unsigned int ssq_count = 0; + +void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length) +{ + for (unsigned int i = 0; i < length; i++) { + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, i)) = seq[i].sp_cmd_ctrl.raw; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, i)) = seq[i].subseq_ctrl.raw; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, i)) = seq[i].sp_cmd_addr.raw; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, i)) = seq[i].addr_update.raw; + } + + ssq_count = length; +} + +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) +{ + /* Should never happen */ + if (ssq_count == 0) + return; + + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); +} + +void iosav_run_once(const int ch) +{ + iosav_run_queue(ch, 1, 0); +} + +void wait_for_iosav(int channel) +{ + while (1) { + if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) + return; + } +} + +void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = gap, + .post_ssq_wait = post, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = wrap, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = post, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = wrap, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_read_mpr_sequence( + int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) +{ + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. In this mode only RD and RDA + * are allowed, and all reads return a predefined pattern. + */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }, + /* DRAM command RD */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops, + .cmd_delay_gap = gap, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops2, + .cmd_delay_gap = 4, + .post_ssq_wait = post2, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops0, + .cmd_delay_gap = gap0, + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = loops0 == 1 ? 0 : 1, + .addr_wrap = loops0 == 1 ? 0 : 18, + }, + }, + /* DRAM command NOP */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = gap1, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }, + /* DRAM command WR */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops2, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = wrap2, + }, + }, + /* DRAM command NOP */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_command_training_sequence( + ramctr_timing *ctrl, int channel, int slotrank, unsigned int address) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = address, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 15, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 0, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = 8, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 326197b9bd..454ba011ab 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -42,6 +42,41 @@ static u32 get_FRQ(const ramctr_timing *ctrl) die("Unsupported CPU or base frequency."); } +/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ +static u8 get_CWL(u32 tCK) +{ + /* Get CWL based on tCK using the following rule */ + switch (tCK) { + case TCK_1333MHZ: + return 12; + + case TCK_1200MHZ: + case TCK_1100MHZ: + return 11; + + case TCK_1066MHZ: + case TCK_1000MHZ: + return 10; + + case TCK_933MHZ: + case TCK_900MHZ: + return 9; + + case TCK_800MHZ: + case TCK_700MHZ: + return 8; + + case TCK_666MHZ: + return 7; + + case TCK_533MHZ: + return 6; + + default: + return 5; + } +} + /* Get REFI based on frequency index, tREFI = 7.8usec */ static u32 get_REFI(u32 FRQ, u8 base_freq) { @@ -655,7 +690,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ printram("CP5a\n"); - err = discover_edges(ctrl); + err = read_mpr_training(ctrl); if (err) return err; @@ -680,8 +715,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ set_read_write_timings(ctrl); - write_controller_mr(ctrl); - if (!s3resume) { err = channel_test(ctrl); if (err) diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 97b8ed9338..1fd7e7590b 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -12,7 +12,6 @@ #include #include #include -#include /* for VbExDisplayScreen() and VbScreenData */ #define _EC_FILENAME(select, suffix) \ (select == VB_SELECT_FIRMWARE_READONLY ? "ecro" suffix : "ecrw" suffix) @@ -401,21 +400,6 @@ static vb2_error_t ec_get_expected_hash(enum vb2_firmware_selection select, * Vboot Callbacks ***********************************************************************/ -/* - * Unsupported. - * - * coreboot does not support the graphics initialization needed to - * display the vboot "wait" screens, etc., because the use case for - * supporting software sync early in the boot flow is to be able to - * quickly update the EC and/or sysjump to RW earlier so that USB-PD - * power (> 15 W) can be negotiated for earlier. - */ -vb2_error_t VbExDisplayScreen(uint32_t screen_type, uint32_t locale, - const VbScreenData *data) -{ - return VB2_ERROR_UNKNOWN; -} - /* * Write opaque data into NV storage region. */ diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 54c82244b6..70c7d77073 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/amd/Kconfig b/src/soc/amd/Kconfig index 7c08f031b0..77eac6ba5a 100644 --- a/src/soc/amd/Kconfig +++ b/src/soc/amd/Kconfig @@ -1,6 +1,5 @@ # Load all chipsets before common -source "src/soc/amd/picasso/Kconfig" -source "src/soc/amd/stoneyridge/Kconfig" +source "src/soc/amd/*/Kconfig" # Load common defaults last -source "src/soc/amd/common/Kconfig" +source "src/soc/amd/common/Kconfig.common" diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig.common similarity index 59% rename from src/soc/amd/common/Kconfig rename to src/soc/amd/common/Kconfig.common index debedac37d..a0836a3372 100644 --- a/src/soc/amd/common/Kconfig +++ b/src/soc/amd/common/Kconfig.common @@ -1,7 +1,7 @@ config SOC_AMD_COMMON bool help - common code for AMD SOCs + common code blocks for AMD SOCs if SOC_AMD_COMMON @@ -9,6 +9,6 @@ config SOC_AMD_PI bool default n -source "src/soc/amd/common/block/Kconfig" +source "src/soc/amd/common/block/*/Kconfig" endif # SOC_AMD_COMMON diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 2a5b42a5ea..c0757c5968 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -1,5 +1 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON),y) - -subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block - -endif +subdirs-$(CONFIG_SOC_AMD_COMMON) += block diff --git a/src/soc/amd/common/block/Kconfig b/src/soc/amd/common/block/Kconfig deleted file mode 100644 index 86150ed870..0000000000 --- a/src/soc/amd/common/block/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -config SOC_AMD_COMMON_BLOCK - bool - help - SoC driver for AMD common IP code - -if SOC_AMD_COMMON_BLOCK - -comment "AMD SoC Common IP Code" -source "src/soc/amd/common/block/*/Kconfig" - -endif diff --git a/src/soc/amd/common/block/Makefile.inc b/src/soc/amd/common/block/Makefile.inc index 33c8822fd6..ad75b92866 100644 --- a/src/soc/amd/common/block/Makefile.inc +++ b/src/soc/amd/common/block/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK),y) +ifeq ($(CONFIG_SOC_AMD_COMMON),y) subdirs-y += ./* diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 24cabfe454..c2bbff440c 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -128,7 +128,7 @@ static const struct device_operations graphics_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_GPU, + PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU, 0, }; diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 54223233db..e7d3260e78 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CALLOUTS_AGESA_H__ -#define __AMD_BLOCK_CALLOUTS_AGESA_H__ +#ifndef AMD_BLOCK_CALLOUTS_AGESA_H +#define AMD_BLOCK_CALLOUTS_AGESA_H #include #include @@ -69,4 +69,4 @@ typedef struct { extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; extern const int BiosCalloutsLen; -#endif /* __AMD_BLOCK_CALLOUTS_AGESA_H__ */ +#endif /* AMD_BLOCK_CALLOUTS_AGESA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 7a9206d009..c6e242adaa 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ACPI_H__ -#define __AMD_BLOCK_ACPI_H__ +#ifndef AMD_BLOCK_ACPI_H +#define AMD_BLOCK_ACPI_H #include #include @@ -44,4 +44,4 @@ void set_pm1cnt_s5(void); void acpi_enable_sci(void); void acpi_disable_sci(void); -#endif /* __AMD_BLOCK_ACPI_H__ */ +#endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 6d96fcd550..932ae47d7d 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMD_BLOCK_ACPIMMIO_H__ -#define __AMD_BLOCK_ACPIMMIO_H__ +#ifndef AMD_BLOCK_ACPIMMIO_H +#define AMD_BLOCK_ACPIMMIO_H #include #include @@ -508,4 +508,4 @@ static inline void aoac_write8(uint8_t reg, uint8_t value) write8(acpimmio_aoac + reg, value); } -#endif /* __AMD_BLOCK_ACPIMMIO_H__ */ +#endif /* AMD_BLOCK_ACPIMMIO_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 0e80ff404c..abf014c325 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMD_BLOCK_ACPIMMIO_MAP_H__ -#define __AMD_BLOCK_ACPIMMIO_MAP_H__ +#ifndef AMD_BLOCK_ACPIMMIO_MAP_H +#define AMD_BLOCK_ACPIMMIO_MAP_H /* * The following AcpiMmio register block mapping represents definitions @@ -132,4 +132,4 @@ #endif -#endif /* __AMD_BLOCK_ACPIMMIO_MAP_H__ */ +#endif /* AMD_BLOCK_ACPIMMIO_MAP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 85505d1c1c..8c08ba01e6 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_AGESAWRAPPER_H__ -#define __AMD_BLOCK_AGESAWRAPPER_H__ +#ifndef AMD_BLOCK_AGESAWRAPPER_H +#define AMD_BLOCK_AGESAWRAPPER_H #include @@ -39,4 +39,4 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params); void set_board_env_params(GNB_ENV_CONFIGURATION *params); void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly); -#endif /* __AMD_BLOCK_AGESAWRAPPER_H__ */ +#endif /* AMD_BLOCK_AGESAWRAPPER_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 7174f5e70b..45bb987fa8 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_AGESAWRAPPER_CALL_H__ -#define __AMD_BLOCK_AGESAWRAPPER_CALL_H__ +#ifndef AMD_BLOCK_AGESAWRAPPER_CALL_H +#define AMD_BLOCK_AGESAWRAPPER_CALL_H #include #include @@ -41,4 +41,4 @@ static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name) return (u32)ret; } -#endif /* __AMD_BLOCK_AGESAWRAPPER_CALL_H__ */ +#endif /* AMD_BLOCK_AGESAWRAPPER_CALL_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h index be1917c932..73373bd6ff 100644 --- a/src/soc/amd/common/block/include/amdblocks/alink.h +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ALINK_H__ -#define __AMD_BLOCK_ALINK_H__ +#ifndef AMD_BLOCK_ALINK_H +#define AMD_BLOCK_ALINK_H #include @@ -32,4 +32,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* __AMD_BLOCK_ALINK_H__ */ +#endif /* AMD_BLOCK_ALINK_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h index 067ff98367..bcac45ab57 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_MMCONF_H__ -#define __AMD_BLOCK_PCI_MMCONF_H__ +#ifndef AMD_BLOCK_PCI_MMCONF_H +#define AMD_BLOCK_PCI_MMCONF_H void enable_pci_mmconf(void); -#endif /* __AMD_BLOCK_PCI_MMCONF_H__ */ +#endif /* AMD_BLOCK_PCI_MMCONF_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index a37c1fdb23..46fcfbfdf1 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_UTIL_H__ -#define __AMD_BLOCK_PCI_UTIL_H__ +#ifndef AMD_BLOCK_PCI_UTIL_H +#define AMD_BLOCK_PCI_UTIL_H #include #include @@ -31,4 +31,4 @@ void write_pci_cfg_irqs(void); void write_pci_int_table(void); const struct irq_idx_name *sb_get_apic_reg_association(size_t *size); -#endif /* __AMD_BLOCK_PCI_UTIL_H__ */ +#endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index a7a73e0353..934a244850 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_BIOSRAM_H__ -#define __AMD_BLOCK_BIOSRAM_H__ +#ifndef AMD_BLOCK_BIOSRAM_H +#define AMD_BLOCK_BIOSRAM_H #include @@ -26,4 +26,4 @@ uint32_t get_uma_size(void); /* Returns the saved UMA base */ uint64_t get_uma_base(void); -#endif /* __AMD_BLOCK_BIOSRAM_H__ */ +#endif /* AMD_BLOCK_BIOSRAM_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h index 055f294625..2f5892463a 100644 --- a/src/soc/amd/common/block/include/amdblocks/car.h +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CAR_H__ -#define __AMD_BLOCK_CAR_H__ +#ifndef AMD_BLOCK_CAR_H +#define AMD_BLOCK_CAR_H #include void ap_teardown_car(uint32_t flags); -#endif /* __AMD_BLOCK_CAR_H__ */ +#endif /* AMD_BLOCK_CAR_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 87944212bd..c1820e2659 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CHIP_H__ -#define __AMD_BLOCK_CHIP_H__ +#ifndef AMD_BLOCK_CHIP_H +#define AMD_BLOCK_CHIP_H #include #include @@ -28,4 +28,4 @@ struct soc_amd_common_config { */ const struct soc_amd_common_config *soc_get_common_config(void); -#endif /* __AMD_BLOCK_CHIP_H__ */ +#endif /* AMD_BLOCK_CHIP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 5bfb4942f2..d5eb617620 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_DIMM_SPD_H__ -#define __AMD_BLOCK_DIMM_SPD_H__ +#ifndef AMD_BLOCK_DIMM_SPD_H +#define AMD_BLOCK_DIMM_SPD_H #include #include @@ -15,4 +15,4 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int sb_read_spd(uint8_t spdAddress, char *buf, size_t len); -#endif /* __AMD_BLOCK_DIMM_SPD_H__ */ +#endif /* AMD_BLOCK_DIMM_SPD_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index c2d822e545..c593e02d49 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ESPI_H__ -#define __AMD_BLOCK_ESPI_H__ +#ifndef AMD_BLOCK_ESPI_H +#define AMD_BLOCK_ESPI_H #include #include @@ -118,4 +118,4 @@ void espi_update_static_bar(uintptr_t bar); */ int espi_setup(void); -#endif /* __AMD_BLOCK_ESPI_H__ */ +#endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 4b2bfddac1..b6162d7e7f 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_GPIO_BANKS_H__ -#define __AMD_BLOCK_GPIO_BANKS_H__ +#ifndef AMD_BLOCK_GPIO_BANKS_H +#define AMD_BLOCK_GPIO_BANKS_H #include @@ -361,4 +361,4 @@ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) /* May be implemented by soc to handle special cases */ void soc_gpio_hook(uint8_t gpio, uint8_t mux); -#endif /* __AMD_BLOCK_GPIO_BANKS_H__ */ +#endif /* AMD_BLOCK_GPIO_BANKS_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h index 55feb6b434..a7a0b84f04 100644 --- a/src/soc/amd/common/block/include/amdblocks/hda.h +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_HDA_H__ -#define __AMD_BLOCK_HDA_H__ +#ifndef AMD_BLOCK_HDA_H +#define AMD_BLOCK_HDA_H #include /* SoC callback to add any quirks to HDA device node in SSDT. */ void hda_soc_ssdt_quirks(const struct device *dev); -#endif /* __AMD_BLOCK_HDA_H__ */ +#endif /* AMD_BLOCK_HDA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h index 92d4002b81..27c8991541 100644 --- a/src/soc/amd/common/block/include/amdblocks/image.h +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_IMAGE_H__ -#define __AMD_BLOCK_IMAGE_H__ +#ifndef AMD_BLOCK_IMAGE_H +#define AMD_BLOCK_IMAGE_H #include void *amd_find_image(const void *start_address, const void *end_address, uint32_t alignment, const char name[8]); -#endif /* __AMD_BLOCK_IMAGE_H__ */ +#endif /* AMD_BLOCK_IMAGE_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 1b69a5b398..fbedb71374 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_LPC_H__ -#define __AMD_BLOCK_LPC_H__ +#ifndef AMD_BLOCK_LPC_H +#define AMD_BLOCK_LPC_H #include @@ -198,4 +198,4 @@ void lpc_set_spibase(uint32_t base); /* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */ void lpc_enable_spi_rom(uint32_t enable); -#endif /* __AMD_BLOCK_LPC_H__ */ +#endif /* AMD_BLOCK_LPC_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/pci_devs.h b/src/soc/amd/common/block/include/amdblocks/pci_devs.h index 8a38ac15d7..074bdd804b 100644 --- a/src/soc/amd/common/block/include/amdblocks/pci_devs.h +++ b/src/soc/amd/common/block/include/amdblocks/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_DEVS_H__ -#define __AMD_BLOCK_PCI_DEVS_H__ +#ifndef AMD_BLOCK_PCI_DEVS_H +#define AMD_BLOCK_PCI_DEVS_H #include @@ -12,4 +12,4 @@ #define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) #endif -#endif /* __AMD_BLOCK_PCI_DEVS_H__ */ +#endif /* AMD_BLOCK_PCI_DEVS_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index f509a5a4df..8cd8236706 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PSP_H__ -#define __AMD_BLOCK_PSP_H__ +#ifndef AMD_BLOCK_PSP_H +#define AMD_BLOCK_PSP_H /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void); @@ -74,4 +74,4 @@ void psp_notify_sx_info(u8 sleep_type); int psp_load_named_blob(enum psp_blob_type type, const char *name); -#endif /* __AMD_BLOCK_PSP_H__ */ +#endif /* AMD_BLOCK_PSP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 7912bd2d45..b825f471a5 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_RESET_H__ -#define __AMD_BLOCK_RESET_H__ +#ifndef AMD_BLOCK_RESET_H +#define AMD_BLOCK_RESET_H #include #include @@ -26,4 +26,4 @@ static inline __noreturn void cold_reset(void) halt(); } -#endif /* __AMD_BLOCK_RESET_H__ */ +#endif /* AMD_BLOCK_RESET_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 6931a5f5cd..f7fce00eef 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_S3_RESUME_H__ -#define __AMD_BLOCK_S3_RESUME_H__ +#ifndef AMD_BLOCK_S3_RESUME_H +#define AMD_BLOCK_S3_RESUME_H #include @@ -9,4 +9,4 @@ AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock); AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); -#endif /* __AMD_BLOCK_S3_RESUME_H__ */ +#endif /* AMD_BLOCK_S3_RESUME_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h index 945b9cd0b4..03e15773cd 100644 --- a/src/soc/amd/common/block/include/amdblocks/sata.h +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_SATA_H__ -#define __AMD_BLOCK_SATA_H__ +#ifndef AMD_BLOCK_SATA_H +#define AMD_BLOCK_SATA_H #include void soc_enable_sata_features(struct device *dev); -#endif /* __AMD_BLOCK_SATA_H__ */ +#endif /* AMD_BLOCK_SATA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/smu.h b/src/soc/amd/common/block/include/amdblocks/smu.h new file mode 100644 index 0000000000..ca5e37a7ee --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_SMU_H +#define AMD_BLOCK_SMU_H + +#include +#include /* SoC-dependent definitions for SMU access */ + +/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ +#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ +#define SMU_DATA_ADDR 0xbc /* 32 bit */ + +/* Arguments indexed locations are contiguous; the number is SoC-dependent */ +#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) + +struct smu_payload { + uint32_t msg[SMU_NUM_ARGS]; +}; + +/* + * Send a message and bi-directional payload to the SMU. The SMU's response, if any, is + * returned via *arg. Returns CB_SUCCESS if success or CB_ERR on failure. + */ +enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload *arg); + +#endif /* AMD_BLOCK_SMU_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 18940a32fc..7da1b24325 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_SPI_H__ -#define __AMD_BLOCK_SPI_H__ +#ifndef AMD_BLOCK_SPI_H +#define AMD_BLOCK_SPI_H #include @@ -108,4 +108,4 @@ void spi_write8(uint8_t reg, uint8_t val); void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); -#endif /* __AMD_BLOCK_SPI_H__ */ +#endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/smu/Kconfig b/src/soc/amd/common/block/smu/Kconfig new file mode 100644 index 0000000000..60c231fae8 --- /dev/null +++ b/src/soc/amd/common/block/smu/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SMU + bool + default n + help + Select this option to add functions to communicate with the SMU to the build. diff --git a/src/soc/amd/common/block/smu/Makefile.inc b/src/soc/amd/common/block/smu/Makefile.inc new file mode 100644 index 0000000000..2afd81abde --- /dev/null +++ b/src/soc/amd/common/block/smu/Makefile.inc @@ -0,0 +1 @@ +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c diff --git a/src/soc/amd/common/block/smu/smu.c b/src/soc/amd/common/block/smu/smu.c new file mode 100644 index 0000000000..4f9c1d1abe --- /dev/null +++ b/src/soc/amd/common/block/smu/smu.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static uint32_t smu_read32(uint32_t reg) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); +} + +static void smu_write32(uint32_t reg, uint32_t val) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); +} + +#define SMU_MESG_RESP_TIMEOUT 0x00 +#define SMU_MESG_RESP_OK 0x01 + +/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ +static int32_t smu_poll_response(bool print_command_duration) +{ + struct stopwatch sw; + const long timeout_ms = 10 * MSECS_PER_SEC; + int32_t result; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + result = smu_read32(REG_ADDR_MESG_RESP); + if (result) { + if (print_command_duration) + printk(BIOS_SPEW, "SMU command consumed %ld usecs\n", + stopwatch_duration_usecs(&sw)); + return result; + } + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + return SMU_MESG_RESP_TIMEOUT; +} + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via + * *arg. + */ +enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload *arg) +{ + size_t i; + + /* wait until SMU can process a new request; don't care if an old request failed */ + if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT) + return CB_ERR; + + /* clear response register */ + smu_write32(REG_ADDR_MESG_RESP, 0); + + /* populate arguments */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); + + /* send message to SMU */ + smu_write32(REG_ADDR_MESG_ID, message_id); + + /* wait until SMU has processed the message and check if it was successful */ + if (smu_poll_response(true) != SMU_MESG_RESP_OK) + return CB_ERR; + + /* copy returned values */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); + + return CB_SUCCESS; +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5ae0a2a58f..4d7d2a6c1a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,7 +29,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -41,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index ac4e23d318..79fdba1267 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -123,19 +123,19 @@ void data_fabric_set_mmio_np(void) static const char *data_fabric_acpi_name(const struct device *dev) { switch (dev->device) { - case PCI_DEVICE_ID_AMD_FAM17H_DF0: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0: return "DFD0"; - case PCI_DEVICE_ID_AMD_FAM17H_DF1: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1: return "DFD1"; - case PCI_DEVICE_ID_AMD_FAM17H_DF2: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2: return "DFD2"; - case PCI_DEVICE_ID_AMD_FAM17H_DF3: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3: return "DFD3"; - case PCI_DEVICE_ID_AMD_FAM17H_DF4: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4: return "DFD4"; - case PCI_DEVICE_ID_AMD_FAM17H_DF5: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5: return "DFD5"; - case PCI_DEVICE_ID_AMD_FAM17H_DF6: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6: return "DFD6"; default: printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); @@ -152,13 +152,13 @@ static struct device_operations data_fabric_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_DF0, - PCI_DEVICE_ID_AMD_FAM17H_DF1, - PCI_DEVICE_ID_AMD_FAM17H_DF2, - PCI_DEVICE_ID_AMD_FAM17H_DF3, - PCI_DEVICE_ID_AMD_FAM17H_DF4, - PCI_DEVICE_ID_AMD_FAM17H_DF5, - PCI_DEVICE_ID_AMD_FAM17H_DF6, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6, 0 }; diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index 545a372100..f812b32a98 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_ACP_H__ -#define __PI_PICASSO_ACP_H__ +#ifndef AMD_PICASSO_ACP_H +#define AMD_PICASSO_ACP_H /* Bus A D0F5 - Audio Processor */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ @@ -11,4 +11,4 @@ #define ACP_PME_EN 0x1418 #define PME_EN_MASK (1 << 0) -#endif /* __PI_PICASSO_ACP_H__ */ +#endif /* AMD_PICASSO_ACP_H */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d3477bb..1f68d78bd8 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_PICASSO_ACPI_H__ -#define __SOC_PICASSO_ACPI_H__ +#ifndef AMD_PICASSO_ACPI_H +#define AMD_PICASSO_ACPI_H #include #include #include +#include +#include unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); @@ -21,4 +23,4 @@ struct chipset_state { struct gpio_wake_state gpio_state; }; -#endif /* __SOC_PICASSO_ACPI_H__ */ +#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index b423f79b0e..7f75de98c5 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,16 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H +#define AMD_PICASSO_AMD_PCI_INT_DEFS_H /* * PIRQ and device routing - these define the index into the * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ -/* - * PIRQ and device routing - these define the index into the - * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. - */ + #define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_A 0x00 /* INT A */ #define PIRQ_B 0x01 /* INT B */ @@ -64,4 +61,4 @@ #define PIRQ_UART3 0x79 /* UART3 */ /* 0x7a-0x7f reserved */ -#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index cbc3929a78..3f6cd247c2 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_CPU_H__ -#define __PICASSO_CPU_H__ +#ifndef AMD_PICASSO_CPU_H +#define AMD_PICASSO_CPU_H int get_cpu_count(void); void check_mca(void); @@ -19,4 +19,4 @@ void check_mca(void); #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ #define RAVEN2_VBIOS_REV 0xc4 -#endif /* __PICASSO_CPU_H__ */ +#endif /* AMD_PICASSO_CPU_H */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 39906e8f95..842cb946a7 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_DATAFABRIC_H__ -#define __SOC_PICASSO_DATAFABRIC_H__ +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H #include @@ -26,4 +26,4 @@ void data_fabric_set_mmio_np(void); -#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ +#endif /* AMD_PICASSO_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 370b29f1e0..4fbb937461 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_GPIO_H__ -#define __PICASSO_GPIO_H__ +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -297,4 +297,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __PICASSO_GPIO_H__ */ +#endif /* AMD_PICASSO_GPIO_H */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index c1dd6ef6ff..3e94a1ad62 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_I2C_H__ -#define __PICASSO_I2C_H__ +#ifndef AMD_PICASSO_I2C_H +#define AMD_PICASSO_I2C_H #include #include @@ -26,4 +26,4 @@ void sb_reset_i2c_slaves(void); /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar); -#endif /* __PICASSO_I2C_H__ */ +#endif /* AMD_PICASSO_I2C_H */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 890b1c3647..a49768f129 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_IOMAP_H__ -#define __SOC_PICASSO_IOMAP_H__ +#ifndef AMD_PICASSO_IOMAP_H +#define AMD_PICASSO_IOMAP_H /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ @@ -90,4 +90,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_PICASSO_IOMAP_H__ */ +#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/memmap.h b/src/soc/amd/picasso/include/soc/memmap.h index c27b165142..53c9d310b0 100644 --- a/src/soc/amd/picasso/include/soc/memmap.h +++ b/src/soc/amd/picasso/include/soc/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_AMD_PICASSO_MEMMAP_H__ -#define __SOC_AMD_PICASSO_MEMMAP_H__ +#ifndef AMD_PICASSO_MEMMAP_H +#define AMD_PICASSO_MEMMAP_H #include #include @@ -16,4 +16,4 @@ struct memmap_early_dram { void memmap_stash_early_dram_usage(void); const struct memmap_early_dram *memmap_get_early_dram_usage(void); -#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */ +#endif /* AMD_PICASSO_MEMMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h index ed63ba86fb..c7fcedbdd9 100644 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ b/src/soc/amd/picasso/include/soc/mrc_cache.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __PICASSO_MRC_CACHE_H__ -#define __PICASSO_MRC_CACHE_H__ +#ifndef AMD_PICASSO_MRC_CACHE_H +#define AMD_PICASSO_MRC_CACHE_H void *soc_fill_mrc_cache(void); void soc_update_mrc_cache(void); -#endif /* __PICASSO_MRC_CACHE_H__ */ +#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0743ba0c9e..841e6a5a0d 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -4,8 +4,8 @@ * The definitions come from the device's PPR. */ -#ifndef SOC_AMD_PICASSO_MSR_H -#define SOC_AMD_PICASSO_MSR_H +#ifndef AMD_PICASSO_MSR_H +#define AMD_PICASSO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ #define PSTATE_DEF_HI_ENABLE_SHIFT 31 @@ -25,4 +25,4 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 -#endif /* SOC_AMD_PICASSO_MSR_H */ +#endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 2abcdd31f7..d5624d4d75 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -6,8 +6,8 @@ * */ -#ifndef __SOC_PICASSO_NVS_H__ -#define __SOC_PICASSO_NVS_H__ +#ifndef AMD_PICASSO_NVS_H +#define AMD_PICASSO_NVS_H #include #include @@ -33,4 +33,4 @@ struct __packed global_nvs { check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_PICASSO_NVS_H__ */ +#endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 83c0bcc7e3..3f18bd5414 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_PCI_DEVS_H__ -#define __PI_PICASSO_PCI_DEVS_H__ +#ifndef AMD_PICASSO_PCI_DEVS_H +#define AMD_PICASSO_PCI_DEVS_H #include #include @@ -118,4 +118,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -#endif /* __PI_PICASSO_PCI_DEVS_H__ */ +#endif /* AMD_PICASSO_PCI_DEVS_H */ diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b338..fc7f14071d 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ -#define __PICASSO_PLATFORM_DESCRIPTORS_H__ +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H #include #include @@ -27,4 +27,4 @@ void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); -#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index afc4d7d1ac..ce197c11e2 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef PSP_VERSTAGE_PSP_TRANSFER_H -#define PSP_VERSTAGE_PSP_TRANSFER_H +#ifndef AMD_PICASSO_PSP_TRANSFER_H +#define AMD_PICASSO_PSP_TRANSFER_H # if (CONFIG_CMOS_RECOVERY_BYTE != 0) # define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE @@ -49,4 +49,4 @@ void show_psp_transfer_info(void); #endif -#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ +#endif /* AMD_PICASSO_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index bb2ee84e03..fb47068ea0 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_RESET_H__ -#define __PI_PICASSO_RESET_H__ +#ifndef AMD_PICASSO_RESET_H +#define AMD_PICASSO_RESET_H void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_PICASSO_RESET_H__ */ +#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 6413c6a06d..1f08efe3ac 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#ifndef AMD_PICASSO_SMI_H +#define AMD_PICASSO_SMI_H #include @@ -221,4 +221,4 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ +#endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index eb7573c52b..2dd0e7b6a2 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -1,40 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SMU_H__ -#define __PICASSO_SMU_H__ - -#include - -/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ -#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ -#define SMU_DATA_ADDR 0xbc /* 32 bit */ +#ifndef AMD_PICASSO_SMU_H +#define AMD_PICASSO_SMU_H +/* + * SMU mailbox register offsets in indirect address space accessed by an index/data pair in + * D0F00 config space. + */ #define REG_ADDR_MESG_ID 0x3b10528 #define REG_ADDR_MESG_RESP 0x3b10564 #define REG_ADDR_MESG_ARGS_BASE 0x3b10998 -/* Argument 0-5 indexed locations are contiguous */ #define SMU_NUM_ARGS 6 -#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) enum smu_message_id { SMC_MSG_S3ENTRY = 0x0c, }; -struct smu_payload { - uint32_t msg[SMU_NUM_ARGS]; -}; - /* - * Send a message and bi-directional payload to the SMU. SMU response, if - * any, is returned via arg. Returns 0 if success or -1 on failure. - */ -enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg); - -/* - * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines - * S-State and SlpTypeEn is clear. Function does not return if successful. + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn gets set by the SMU. Function does not return if successful. */ void smu_sx_entry(void); -#endif /* __PICASSO_SMU_H__ */ +#endif /* AMD_PICASSO_SMU_H */ diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 0de0643249..e03a78e8da 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SOC_UTIL_H__ -#define __PICASSO_SOC_UTIL_H__ +#ifndef AMD_PICASSO_SOC_UTIL_H +#define AMD_PICASSO_SOC_UTIL_H #include @@ -39,4 +39,4 @@ bool soc_is_reduced_io_sku(void); /* function to determine the iGPU type */ bool soc_is_raven2(void); -#endif /* __PICASSO_SOC_UTIL_H__ */ +#endif /* AMD_PICASSO_SOC_UTIL_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 222858ab51..d193661985 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SB_H__ -#define __PICASSO_SB_H__ +#ifndef AMD_PICASSO_SOUTHBRIDGE_H +#define AMD_PICASSO_SOUTHBRIDGE_H #include #include @@ -294,4 +294,4 @@ void i2c_soc_init(void); /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings); -#endif /* __PICASSO_SB_H__ */ +#endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 4e5619fa86..051c8bf4d5 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_UART_H__ -#define __PICASSO_UART_H__ +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H #include @@ -10,4 +10,4 @@ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART * uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ -#endif /* __PICASSO_UART_H__ */ +#endif /* AMD_PICASSO_UART_H */ diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld index eeb6dda0cf..369d43151e 100644 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ b/src/soc/amd/picasso/memlayout_x86.ld @@ -97,7 +97,20 @@ SECTIONS } #if ENV_BOOTBLOCK -/* Bootblock specific scripts which provide more SECTION directives. */ -#include -#include + +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +SECTIONS { + /* Trigger an error if I have an unusable start address */ + _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + . = CONFIG_X86_RESET_VECTOR; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} #endif /* ENV_BOOTBLOCK */ diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 96d33f2f1f..3c3021e086 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -48,8 +48,8 @@ static struct device_operations internal_pcie_gpp_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA, - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, 0 }; @@ -72,5 +72,5 @@ static struct device_operations external_pcie_gpp_ops = { static const struct pci_driver external_pcie_gpp_driver __pci_driver = { .ops = &external_pcie_gpp_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, + .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, }; diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 902538ff6c..7a0074c091 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c index 4a373ce273..1496957117 100644 --- a/src/soc/amd/picasso/smu.c +++ b/src/soc/amd/picasso/smu.c @@ -1,86 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include -#include +#include #include -#include - -static uint32_t smu_read32(uint32_t reg) -{ - pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); - return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); -} - -static void smu_write32(uint32_t reg, uint32_t val) -{ - pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); - pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); -} - -#define SMU_MESG_RESP_TIMEOUT 0x00 -#define SMU_MESG_RESP_OK 0x01 - -/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ -static int32_t smu_poll_response(bool print_command_duration) -{ - struct stopwatch sw; - const long timeout_ms = 10 * MSECS_PER_SEC; - int32_t result; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - result = smu_read32(REG_ADDR_MESG_RESP); - if (result) { - if (print_command_duration) - printk(BIOS_SPEW, "SMU command consumed %ld usecs\n", - stopwatch_duration_usecs(&sw)); - return result; - } - } while (!stopwatch_expired(&sw)); - - printk(BIOS_ERR, "Error: timeout sending SMU message\n"); - return SMU_MESG_RESP_TIMEOUT; -} - -/* - * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via - * arg. - */ -enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) -{ - size_t i; - - /* wait until SMU can process a new request; don't care if an old request failed */ - if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT) - return CB_ERR; - - /* clear response register */ - smu_write32(REG_ADDR_MESG_RESP, 0); - - /* populate arguments */ - for (i = 0 ; i < SMU_NUM_ARGS ; i++) - smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); - - /* send message to SMU */ - smu_write32(REG_ADDR_MESG_ID, id); - - /* wait until SMU has processed the message and check if it was successful */ - if (smu_poll_response(true) != SMU_MESG_RESP_OK) - return CB_ERR; - - /* copy returned values */ - for (i = 0 ; i < SMU_NUM_ARGS ; i++) - arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); - - return CB_SUCCESS; -} /* * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and - * SlpTypeEn is clear. Function does not return if successful. + * SlpTypeEn gets set by the SMU. Function does not return if successful. */ void smu_sx_entry(void) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0e32005fb0..86df3610e8 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_LFENCE select SOC_AMD_PI select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 9617b45eca..19f0c81136 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef AMD_STONEYRIDGE_ACPI_H +#define AMD_STONEYRIDGE_ACPI_H #include @@ -16,4 +16,4 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, const char *soc_acpi_name(const struct device *dev); -#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index c32786322c..3b54076ddd 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H +#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H /* * PIRQ and device routing - these define the index into the @@ -44,4 +44,4 @@ #define PIRQ_UART0 0x74 #define PIRQ_UART1 0x75 -#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 8d25fb6d4e..528daa4125 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef AMD_STONEYRIDGE_CPU_H +#define AMD_STONEYRIDGE_CPU_H /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest @@ -16,4 +16,4 @@ void check_mca(void); -#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* AMD_STONEYRIDGE_CPU_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 02cc1884a5..8bfb1f606b 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef AMD_STONEYRIDGE_GPIO_H +#define AMD_STONEYRIDGE_GPIO_H #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -292,4 +292,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* AMD_STONEYRIDGE_GPIO_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 63db7d4b16..0b61329fef 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_I2C_H__ -#define __STONEYRIDGE_I2C_H__ +#ifndef AMD_STONEYRIDGE_I2C_H +#define AMD_STONEYRIDGE_I2C_H #include #include @@ -29,4 +29,4 @@ struct soc_amd_i2c_save { void sb_reset_i2c_slaves(void); -#endif /* __STONEYRIDGE_I2C_H__ */ +#endif /* AMD_STONEYRIDGE_I2C_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 8056287d4f..432888028a 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef AMD_STONEYRIDGE_IOMAP_H +#define AMD_STONEYRIDGE_IOMAP_H /* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -51,4 +51,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* AMD_STONEYRIDGE_IOMAP_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 3b5fd22969..d00f5660d7 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H +#define AMD_STONEYRIDGE_NORTHBRIDGE_H #include #include @@ -89,4 +89,4 @@ void fam15_finalize(void *chip_info); void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 03a12336f7..6af657feb3 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef AMD_STONEYRIDGE_PCI_DEVS_H +#define AMD_STONEYRIDGE_PCI_DEVS_H #include #include @@ -201,4 +201,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6dc0b721a7..1cbaeec831 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef AMD_STONEYRIDGE_ROMSTAGE_H +#define AMD_STONEYRIDGE_ROMSTAGE_H void mainboard_romstage_entry_s3(int s3_resume); -#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 15bba0fd9b..60a91d087a 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef AMD_STONEYRIDGE_SMI_H +#define AMD_STONEYRIDGE_SMI_H #define SMI_GEVENTS 24 #define SCIMAPS 58 @@ -218,4 +218,4 @@ void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* AMD_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 85df0b3b3a..cbd9caad95 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H +#define AMD_STONEYRIDGE_SOUTHBRIDGE_H #include #include @@ -349,4 +349,4 @@ void i2c_soc_early_init(void); /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); -#endif /* __STONEYRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */ diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ee1a543728..d0e7a73a3f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -185,24 +185,16 @@ static unsigned long soc_fill_dmar(unsigned long current) /* DEFVTBAR has to be set and enabled. */ if (defvtbar && defvten) { tmp = current; - /* - * P2SB may already be hidden. There's no clear rule, when. - * It is needed to get bus, device and function for IOAPIC and - * HPET device which is stored in P2SB device. So unhide it to - * get the info and hide it again when done. - */ - p2sb_unhide(); - struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); - uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); - uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + union p2sb_bdf ibdf = p2sb_get_ioapic_bdf(); + union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); p2sb_hide(); current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + 2, ibdf.bus, ibdf.dev, ibdf.fn); current += acpi_create_dmar_ds_msi_hpet(current, - 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + 0, hbdf.bus, hbdf.dev, hbdf.fn); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 6cfce43a81..4a791ef181 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -27,11 +27,11 @@ void *cbmem_top_chipset(void) /* * +-------------------------+ Top of RAM (aligned) * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE + * | code and data | Length: CONFIG_SMM_TSEG_SIZE * | (TSEG) | * +-------------------------+ SMM base (aligned) * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | Chipset Reserved Memory | Length: Multiple of CONFIG_SMM_TSEG_SIZE * | | * +-------------------------+ top_of_ram (aligned) * | | diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7ee69908f8..7d21665138 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -17,11 +17,11 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +ramstage-y += northbridge.c ramstage-y += pei_data.c romstage-y += pei_data.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += systemagent.c CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/northbridge.c similarity index 100% rename from src/soc/intel/broadwell/systemagent.c rename to src/soc/intel/broadwell/northbridge.c diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index a6511982de..ee6ce68c1f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -20,23 +20,58 @@ config SOC_INTEL_CSE_LITE_SKU help Enables CSE Lite SKU +config SOC_INTEL_CSE_RW_UPDATE + bool "Enable the CSE RW Update Feature" + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + This config will enable CSE RW firmware update feature and also will be used ensure + all the required configs are provided by mainboard. + +if SOC_INTEL_CSE_RW_UPDATE config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" - depends on SOC_INTEL_CSE_LITE_SKU default "SI_ME" help Name of CSE region in FMAP +config SOC_INTEL_CSE_RW_A_FMAP_NAME + string "Location of CSE RW A in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU + default "ME_RW_A" + help + Name of CSE RW A region in FMAP + +config SOC_INTEL_CSE_RW_B_FMAP_NAME + string "Location of CSE RW B in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU + default "ME_RW_B" + help + Name of CSE RW B region in FMAP + config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" - depends on SOC_INTEL_CSE_LITE_SKU default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS name for CSE RW metadata file" + default "me_rw.metadata" + help + CBFS name for Intel CSE CBFS RW metadata file + config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" - depends on SOC_INTEL_CSE_LITE_SKU default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_VERSION + string "Intel CSE RW firmware version" + default "" + help + This config contains the Intel CSE RW version of the blob that is provided by + SOC_INTEL_CSE_RW_FILE config and the version must be set in the format + major.minor.hotfix.build (ex: 14.0.40.1209). +endif diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c20d1..d2f94a41a9 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -4,11 +4,41 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B +regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ + $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) cbfs-files-y += $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +else +$(error "CSE RW file path is missing and need to be set by mainboard config") +endif + +# Extract the CSE RW firmware version and update the cse_rw_metadata structure +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") +CSE_RW_VERSION:=$(subst ., ,$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))) +MAJOR := $(word 1, $(CSE_RW_VERSION)) +MINOR := $(word 2, $(CSE_RW_VERSION)) +HOTFIX := $(word 3, $(CSE_RW_VERSION)) +BUILD := $(word 4, $(CSE_RW_VERSION)) +CPPFLAGS_common += -DCSE_RW_MAJOR=$(MAJOR) -DCSE_RW_MINOR=$(MINOR) -DCSE_RW_HOTFIX=$(HOTFIX) -DCSE_RW_BUILD=$(BUILD) +else +$(error "CSE RW version is missing and need to be set by mainboard config") +endif + +# Compute the hash of the CSE RW binary and update the cse_rw_metadata structure +CSE_RW_PATH := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +HASH := $(shell openssl dgst -sha256 -hex $(CSE_RW_PATH) | cut -d " " -f2 | fold -w2 | paste -sd',' -) +CPPFLAGS_common += -DCSE_RW_SHA256=$(HASH) + +# Add the CSE RW metadata file to FW_MAIN_A/B +CSE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_RW_METADATA) +$(CSE_RW_METADATA)-file := cse_rw_metadata.c:struct +$(CSE_RW_METADATA)-name := $(CSE_RW_METADATA) +$(CSE_RW_METADATA)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef6db3da4f..d10492bbe0 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -555,6 +555,9 @@ int heci_reset(void) { uint32_t csr; + /* Clear post code to prevent eventlog entry from unknown code. */ + post_code(0); + /* Send reset request */ csr = read_host_csr(); csr |= (CSR_RESET | CSR_IG); diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f470..9c498b536f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -9,12 +9,8 @@ #include #include #include -#include #include -/* CSE RW version size reserved in the CSE CBFS RW binary */ -#define CSE_RW_VERSION_SZ 16 - /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -45,6 +41,10 @@ enum boot_partition_id { /* CSE recovery sub-error codes */ enum csme_failure_reason { + + /* No error */ + CSE_LITE_SKU_NO_ERROR = 0, + /* Unspecified error */ CSE_LITE_SKU_UNSPECIFIED = 1, @@ -64,7 +64,16 @@ enum csme_failure_reason { CSE_LITE_SKU_COMMUNICATION_ERROR = 6, /* Fails to wipe CSE runtime data */ - CSE_LITE_SKU_DATA_WIPE_ERROR = 7 + CSE_LITE_SKU_DATA_WIPE_ERROR = 7, + + /* CSE RW is not found */ + CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, + + /* CSE CBFS RW SHA-256 mismatch with the provided SHA */ + CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9, + + /* CSE CBFS RW metadata is not found */ + CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10, }; /* @@ -110,14 +119,6 @@ enum bp_info_flags { BP_INFO_READ_ONLY_CFG = 1 << 2, }; -/* Boot Partition FW Version */ -struct fw_version { - uint16_t major; - uint16_t minor; - uint16_t hotfix; - uint16_t build; -} __packed; - /* CSE boot partition entry info */ struct cse_bp_entry { /* Boot partition version */ @@ -191,49 +192,6 @@ static const struct cse_bp_entry *cse_get_bp_entry(enum boot_partition_id bp, return &cse_bp_info->bp_entries[bp]; } -static void cse_get_bp_entry_range(const struct cse_bp_info *cse_bp_info, - enum boot_partition_id bp, uint32_t *start_offset, uint32_t *end_offset) -{ - const struct cse_bp_entry *cse_bp; - - cse_bp = cse_get_bp_entry(bp, cse_bp_info); - - if (start_offset) - *start_offset = cse_bp->start_offset; - - if (end_offset) - *end_offset = cse_bp->end_offset; - -} - -static const struct fw_version *cse_get_bp_entry_version(enum boot_partition_id bp, - const struct cse_bp_info *bp_info) -{ - const struct cse_bp_entry *cse_bp; - - cse_bp = cse_get_bp_entry(bp, bp_info); - return &cse_bp->fw_ver; -} - -static const struct fw_version *cse_get_rw_version(const struct cse_bp_info *cse_bp_info) -{ - return cse_get_bp_entry_version(RW, cse_bp_info); -} - -static bool cse_is_rw_bp_status_valid(const struct cse_bp_info *cse_bp_info) -{ - const struct cse_bp_entry *rw_bp; - - rw_bp = cse_get_bp_entry(RW, cse_bp_info); - - if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || - rw_bp->status == BP_STATUS_GENERAL_FAILURE) { - printk(BIOS_ERR, "cse_lite: RW BP (status:%u) is not valid\n", rw_bp->status); - return false; - } - return true; -} - static void cse_print_boot_partition_info(const struct cse_bp_info *cse_bp_info) { const struct cse_bp_entry *cse_bp; @@ -369,6 +327,44 @@ static bool cse_set_next_boot_partition(enum boot_partition_id bp) return true; } +static bool cse_data_clear_request(const struct cse_bp_info *cse_bp_info) +{ + struct data_clr_request { + struct mkhi_hdr hdr; + uint8_t reserved[4]; + } __packed; + + struct data_clr_request data_clr_rq = { + .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, + .hdr.command = MKHI_BUP_COMMON_DATA_CLEAR, + .reserved = {0}, + }; + + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_soft_temp_disable() || + cse_get_current_bp(cse_bp_info) != RO) { + printk(BIOS_ERR, "cse_lite: CSE doesn't meet DATA CLEAR cmd prerequisites\n"); + return false; + } + + printk(BIOS_DEBUG, "cse_lite: Sending DATA CLEAR HECI command\n"); + + struct mkhi_hdr data_clr_rsp; + size_t data_clr_rsp_sz = sizeof(data_clr_rsp); + + if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, + &data_clr_rsp_sz)) { + return false; + } + + if (data_clr_rsp.result) { + printk(BIOS_ERR, "cse_lite: CSE DATA CLEAR command response failed: %d\n", + data_clr_rsp.result); + return false; + } + + return true; +} + __weak void cse_board_reset(void) { /* Default weak implementation, does nothing. */ @@ -400,6 +396,80 @@ static bool cse_boot_to_rw(const struct cse_bp_info *cse_bp_info) return cse_set_and_boot_from_next_bp(RW); } +/* Check if CSE RW data partition is valid or not */ +static bool cse_is_rw_dp_valid(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *rw_bp; + + rw_bp = cse_get_bp_entry(RW, cse_bp_info); + return rw_bp->status != BP_STATUS_DATA_FAILURE; +} + +/* + * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE + * otherwise false if any operation fails. + */ +static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info) +{ + /* + * If RW partition status indicates BP_STATUS_DATA_FAILURE, + * - Send DATA CLEAR HECI command to CSE + * - Send SET BOOT PARTITION INFO(RW) command to set CSE's next partition + * - Issue GLOBAL RESET HECI command. + */ + if (cse_is_rw_dp_valid(cse_bp_info)) + return true; + + if (!cse_data_clear_request(cse_bp_info)) + return false; + + return cse_boot_to_rw(cse_bp_info); +} + +#if CONFIG(SOC_INTEL_CSE_RW_UPDATE) +static const struct fw_version *cse_get_bp_entry_version(enum boot_partition_id bp, + const struct cse_bp_info *bp_info) +{ + const struct cse_bp_entry *cse_bp; + + cse_bp = cse_get_bp_entry(bp, bp_info); + return &cse_bp->fw_ver; +} + +static const struct fw_version *cse_get_rw_version(const struct cse_bp_info *cse_bp_info) +{ + return cse_get_bp_entry_version(RW, cse_bp_info); +} + +static void cse_get_bp_entry_range(const struct cse_bp_info *cse_bp_info, + enum boot_partition_id bp, uint32_t *start_offset, uint32_t *end_offset) +{ + const struct cse_bp_entry *cse_bp; + + cse_bp = cse_get_bp_entry(bp, cse_bp_info); + + if (start_offset) + *start_offset = cse_bp->start_offset; + + if (end_offset) + *end_offset = cse_bp->end_offset; + +} + +static bool cse_is_rw_bp_status_valid(const struct cse_bp_info *cse_bp_info) +{ + const struct cse_bp_entry *rw_bp; + + rw_bp = cse_get_bp_entry(RW, cse_bp_info); + + if (rw_bp->status == BP_STATUS_PARTITION_NOT_PRESENT || + rw_bp->status == BP_STATUS_GENERAL_FAILURE) { + printk(BIOS_ERR, "cse_lite: RW BP (status:%u) is not valid\n", rw_bp->status); + return false; + } + return true; +} + static bool cse_boot_to_ro(const struct cse_bp_info *cse_bp_info) { if (cse_get_current_bp(cse_bp_info) == RO) @@ -412,24 +482,13 @@ static bool cse_get_rw_rdev(struct region_device *rdev) { if (fmap_locate_area_as_rdev_rw(CONFIG_SOC_INTEL_CSE_FMAP_NAME, rdev) < 0) { printk(BIOS_ERR, "cse_lite: Failed to locate %s in FMAP\n", - CONFIG_SOC_INTEL_CSE_FMAP_NAME); + CONFIG_SOC_INTEL_CSE_FMAP_NAME); return false; } return true; } -static bool cse_get_cbfs_rdev(struct region_device *source_rdev) -{ - struct cbfsf file_desc; - - if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) - return false; - - cbfs_file_data(source_rdev, &file_desc); - return true; -} - static bool cse_is_rw_bp_sign_valid(const struct region_device *target_rdev) { uint32_t cse_bp_sign; @@ -465,53 +524,35 @@ static bool cse_get_target_rdev(const struct cse_bp_info *cse_bp_info, return true; } -static bool cse_data_clear_request(const struct cse_bp_info *cse_bp_info) +static const char *cse_get_source_rdev_fmap(void) { - struct data_clr_request { - struct mkhi_hdr hdr; - uint8_t reserved[4]; - } __packed; + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + return NULL; - struct data_clr_request data_clr_rq = { - .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, - .hdr.command = MKHI_BUP_COMMON_DATA_CLEAR, - .reserved = {0}, - }; + if (vboot_is_firmware_slot_a(ctx)) + return CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME; - if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_soft_temp_disable() || - cse_get_current_bp(cse_bp_info) != RO) { - printk(BIOS_ERR, "cse_lite: CSE doesn't meet DATA CLEAR cmd prerequisites\n"); - return false; - } - - printk(BIOS_DEBUG, "cse_lite: Sending DATA CLEAR HECI command\n"); - - struct mkhi_hdr data_clr_rsp; - size_t data_clr_rsp_sz = sizeof(data_clr_rsp); - - if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, - &data_clr_rsp_sz)) { - return false; - } - - if (data_clr_rsp.result) { - printk(BIOS_ERR, "cse_lite: CSE DATA CLEAR command response failed: %d\n", - data_clr_rsp.result); - return false; - } - - return true; + return CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME; } -static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, - void *cse_cbfs_rw_ver) +static bool cse_get_source_rdev(struct region_device *rdev) { + const char *reg_name; + uint32_t cbfs_type = CBFS_TYPE_RAW; + struct cbfsf fh; - if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) - != sizeof(struct fw_version)) { - printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); + reg_name = cse_get_source_rdev_fmap(); + + if (reg_name == NULL) return false; - } + + if (cbfs_locate_file_in_region(&fh, reg_name, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, + &cbfs_type) < 0) + return false; + + cbfs_file_data(rdev, &fh); + return true; } @@ -522,60 +563,49 @@ static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_rw_metadata *source_metadata) { - struct fw_version cse_cbfs_rw_ver; const struct fw_version *cse_rw_ver; - if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) - return false; - printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - cse_cbfs_rw_ver.major, - cse_cbfs_rw_ver.minor, - cse_cbfs_rw_ver.hotfix, - cse_cbfs_rw_ver.build); + source_metadata->version.major, + source_metadata->version.minor, + source_metadata->version.hotfix, + source_metadata->version.build); cse_rw_ver = cse_get_rw_version(cse_bp_info); - if (cse_cbfs_rw_ver.major != cse_rw_ver->major) - return cse_cbfs_rw_ver.major - cse_rw_ver->major; - else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) - return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; - else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) - return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + if (source_metadata->version.major != cse_rw_ver->major) + return source_metadata->version.major - cse_rw_ver->major; + else if (source_metadata->version.minor != cse_rw_ver->minor) + return source_metadata->version.minor - cse_rw_ver->minor; + else if (source_metadata->version.hotfix != cse_rw_ver->hotfix) + return source_metadata->version.hotfix - cse_rw_ver->hotfix; else - return cse_cbfs_rw_ver.build - cse_rw_ver->build; + return source_metadata->version.build - cse_rw_ver->build; } -/* Check if CSE RW data partition is valid or not */ -static bool cse_is_rw_dp_valid(const struct cse_bp_info *cse_bp_info) +/* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ +static bool cse_verify_cbfs_rw_sha256(const uint8_t *expected_rw_blob_sha, + const void *rw_blob, const size_t rw_blob_sz) + { - const struct cse_bp_entry *rw_bp; + uint8_t rw_comp_sha[VB2_SHA256_DIGEST_SIZE]; - rw_bp = cse_get_bp_entry(RW, cse_bp_info); - return rw_bp->status != BP_STATUS_DATA_FAILURE; -} - -/* - * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE - * otherwise false if any operation fails. - */ -static bool cse_fix_data_failure_err(const struct cse_bp_info *cse_bp_info) -{ - /* - * If RW partition status indicates BP_STATUS_DATA_FAILURE, - * - Send DATA CLEAR HECI command to CSE - * - Send SET BOOT PARTITION INFO(RW) command to set CSE's next partition - * - Issue GLOBAL RESET HECI command. - */ - if (cse_is_rw_dp_valid(cse_bp_info)) - return true; - - if (!cse_data_clear_request(cse_bp_info)) + if (vb2_digest_buffer(rw_blob, rw_blob_sz, VB2_HASH_SHA256, rw_comp_sha, + VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: CSE CBFS RW's SHA-256 calculation has failed\n"); return false; + } - return cse_boot_to_rw(cse_bp_info); + if (memcmp(expected_rw_blob_sha, rw_comp_sha, VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: Computed CBFS RW's SHA-256 does not match with" + "the provided SHA in the metadata\n"); + return false; + } + printk(BIOS_SPEW, "cse_lite: Computed SHA of CSE CBFS RW Image matches the" + " provided hash in the metadata\n"); + return true; } static bool cse_erase_rw_region(const struct region_device *target_rdev) @@ -587,8 +617,8 @@ static bool cse_erase_rw_region(const struct region_device *target_rdev) return true; } -static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, - size_t size) +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, + size_t offset, size_t size) { if (rdev_writeat(target_rdev, buf, offset, size) < 0) { printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); @@ -599,69 +629,63 @@ static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf } static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_rw_metadata *source_metadata) { - return !cse_check_version_mismatch(cse_bp_info, source_rdev); + return !cse_check_version_mismatch(cse_bp_info, source_metadata); } static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_rw_metadata *source_metadata) { - return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; + return cse_check_version_mismatch(cse_bp_info, source_metadata) < 0; } static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + const struct cse_rw_metadata *source_metadata, + struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_rdev)); + !cse_is_rw_version_latest(cse_bp_info, source_metadata)); } static bool cse_write_rw_region(const struct region_device *target_rdev, - const struct region_device *source_rdev) + const void *cse_cbfs_rw, const size_t cse_cbfs_rw_sz) { - void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, - region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); - /* Points to CSE CBFS RW image after boot partition signature */ uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; /* Size of CSE CBFS RW image without boot partition signature */ - uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - - (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + uint32_t cse_cbfs_rw_wo_sign_sz = cse_cbfs_rw_sz - CSE_RW_SIGN_SIZE; /* Update except CSE RW signature */ if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, cse_cbfs_rw_wo_sign_sz)) - goto exit_rw_update; + return false; /* Update CSE RW signature to indicate update is complete */ if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) - goto exit_rw_update; - - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return true; - -exit_rw_update: - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return false; -} - -static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) -{ - if (!cse_erase_rw_region(target_rdev)) - return false; - - if (!cse_write_rw_region(target_rdev, source_rdev)) return false; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); return true; } +static enum csme_failure_reason cse_update_rw(const struct cse_bp_info *cse_bp_info, + const void *cse_cbfs_rw, const size_t cse_blob_sz, + struct region_device *target_rdev) +{ + + if (!cse_erase_rw_region(target_rdev)) + return CSE_LITE_SKU_FW_UPDATE_ERROR; + + if (!cse_write_rw_region(target_rdev, cse_cbfs_rw, cse_blob_sz)) + return CSE_LITE_SKU_FW_UPDATE_ERROR; + + return CSE_LITE_SKU_NO_ERROR; +} + static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_rw_metadata *source_metadata) { /* * To set CSE's operation mode to HMRFPO mode: @@ -671,7 +695,7 @@ static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + if (cse_is_downgrade_instance(cse_bp_info, source_metadata) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); return false; @@ -680,31 +704,62 @@ static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, return cse_hmrfpo_enable(); } -static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct cse_rw_metadata *source_metadata, + struct region_device *target_rdev) { - if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) - return CSE_LITE_SKU_COMMUNICATION_ERROR; + struct region_device source_rdev; + enum csme_failure_reason rv; - if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) - return CSE_LITE_SKU_FW_UPDATE_ERROR; + if (!cse_get_source_rdev(&source_rdev)) + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; - return 0; + void *cse_cbfs_rw = rdev_mmap_full(&source_rdev); + + if (!cse_cbfs_rw) { + printk(BIOS_ERR, "cse_lite: CSE CBFS RW blob could not be mapped\n"); + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; + } + + if (!cse_verify_cbfs_rw_sha256(source_metadata->sha256, cse_cbfs_rw, + region_device_sz(&source_rdev))) { + rv = CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH; + goto error_exit; + } + + if (!cse_prep_for_rw_update(cse_bp_info, source_metadata)) { + rv = CSE_LITE_SKU_COMMUNICATION_ERROR; + goto error_exit; + } + + rv = cse_update_rw(cse_bp_info, cse_cbfs_rw, region_device_sz(&source_rdev), + target_rdev); + +error_exit: + rdev_munmap(&source_rdev, cse_cbfs_rw); + return rv; } -static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) +static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info) { struct region_device target_rdev; + struct cse_rw_metadata source_metadata; + + /* Read CSE CBFS RW metadata */ + if (cbfs_boot_load_file(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, + sizeof(source_metadata), CBFS_TYPE_RAW) != sizeof(source_metadata)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE CBFS RW metadata\n"); + return CSE_LITE_SKU_RW_METADATA_NOT_FOUND; + } if (!cse_get_target_rdev(cse_bp_info, &target_rdev)) { printk(BIOS_ERR, "cse_lite: Failed to get CSE RW Partition\n"); return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + if (cse_is_update_required(cse_bp_info, &source_metadata, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_metadata, &target_rdev); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -712,6 +767,7 @@ static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, return 0; } +#endif void cse_fw_sync(void *unused) { @@ -736,14 +792,16 @@ void cse_fw_sync(void *unused) if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); - /* If RW blob is present in CBFS, then trigger CSE firmware update */ + /* + * If SOC_INTEL_CSE_RW_UPDATE is defined , then trigger CSE firmware update. The driver + * triggers recovery if CSE CBFS RW metadata or CSE CBFS RW blob is not available. + */ +#if CONFIG(SOC_INTEL_CSE_RW_UPDATE) uint8_t rv; - struct region_device source_rdev; - if (cse_get_cbfs_rdev(&source_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); - if (rv) - cse_trigger_recovery(rv); - } + rv = cse_fw_update(&cse_bp_info.bp_info); + if (rv) + cse_trigger_recovery(rv); +#endif if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n"); diff --git a/src/soc/intel/common/block/cse/cse_rw_metadata.c b/src/soc/intel/common/block/cse/cse_rw_metadata.c new file mode 100644 index 0000000000..3f7e779907 --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_rw_metadata.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define HASH_TO_ARRAY(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16,\ + x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30,\ + x31, x32) { 0x##x1, 0x##x2, 0x##x3, 0x##x4, 0x##x5, 0x##x6, 0x##x7,\ + 0x##x8, 0x##x9, 0x##x10, 0x##x11, 0x##x12, 0x##x13, 0x##x14, 0x##x15,\ + 0x##x16, 0x##x17, 0x##x18, 0x##x19, 0x##x20, 0x##x21, 0x##x22, 0x##x23,\ + 0x##x24, 0x##x25, 0x##x26, 0x##x27, 0x##x28, 0x##x29, 0x##x30, 0x##x31,\ + 0x##x32 } +#define HASH_BYTEARRAY(...) HASH_TO_ARRAY(__VA_ARGS__) + +/* + * This structure contains the CSE RW version and hash details which are filled during the + * compile time. + * Makefile will extract the following details and updates the structure variable via the + * compile time flags. + * CSE RW version: Extract the version string from the SOC_INTEL_CSE_RW_VERSION config and + * assign the major, minor, hotfix and build versions. + * CSE RW hash: Compute the hash of CSE RW binary in hex format using the openssl and use the + * HASH_BYTEARRAY macro to convert the 64 character hex values into the array. + */ +struct cse_rw_metadata metadata = { + .version = { + .major = CSE_RW_MAJOR, + .minor = CSE_RW_MINOR, + .build = CSE_RW_BUILD, + .hotfix = CSE_RW_HOTFIX, + }, + .sha256 = HASH_BYTEARRAY(CSE_RW_SHA256), +}; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f554933ef4..64ee0ddd06 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -4,6 +4,7 @@ #define SOC_INTEL_COMMON_CSE_H #include +#include /* MKHI Command groups */ #define MKHI_GROUP_ID_CBM 0x0 @@ -61,6 +62,24 @@ struct mkhi_hdr { uint8_t result; } __packed; +/* CSE FW Version */ +struct fw_version { + uint16_t major; + uint16_t minor; + uint16_t hotfix; + uint16_t build; +} __packed; + +/* + * CSE RW metadata structure + * fw_version - CSE RW firmware version + * sha256 - Hash of the CSE RW binary. + */ +struct cse_rw_metadata { + struct fw_version version; + uint8_t sha256[VB2_SHA256_DIGEST_SIZE]; +}; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 71f9c6255d..436861c924 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -29,6 +29,21 @@ void p2sb_disable_sideband_access(void); void p2sb_enable_bar(void); void p2sb_configure_hpet(void); +union p2sb_bdf { + struct { + uint16_t fn : 3; + uint16_t dev : 5; + uint16_t bus : 8; + }; + uint16_t raw; +}; + +union p2sb_bdf p2sb_get_hpet_bdf(void); +void p2sb_set_hpet_bdf(union p2sb_bdf bdf); +union p2sb_bdf p2sb_get_ioapic_bdf(void); +void p2sb_set_ioapic_bdf(union p2sb_bdf bdf); + + /* SOC overrides */ /* * Each SoC should implement EP Mask register to disable SB access diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index a1330abdd9..d557e36833 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index d97cd8d2d4..05bef2bc4e 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -15,6 +15,18 @@ #define HIDE_BIT (1 << 0) +static bool p2sb_is_hidden(void) +{ + const uint16_t pci_vid = pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID); + + if (pci_vid == 0xffff) + return true; + if (pci_vid == PCI_VENDOR_ID_INTEL) + return false; + printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n"); + return true; +} + void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ @@ -42,6 +54,44 @@ void p2sb_configure_hpet(void) pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); } +union p2sb_bdf p2sb_get_hpet_bdf(void) +{ + const bool was_hidden = p2sb_is_hidden(); + if (was_hidden) + p2sb_unhide(); + + union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF) }; + + if (was_hidden) + p2sb_hide(); + + return bdf; +} + +void p2sb_set_hpet_bdf(union p2sb_bdf bdf) +{ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw); +} + +union p2sb_bdf p2sb_get_ioapic_bdf(void) +{ + const bool was_hidden = p2sb_is_hidden(); + if (was_hidden) + p2sb_unhide(); + + union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF) }; + + if (was_hidden) + p2sb_hide(); + + return bdf; +} + +void p2sb_set_ioapic_bdf(union p2sb_bdf bdf) +{ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, bdf.raw); +} + static void p2sb_set_hide_bit(int hide) { const uint16_t reg = PCH_P2SB_E0 + 1; @@ -59,8 +109,7 @@ void p2sb_unhide(void) { p2sb_set_hide_bit(0); - if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != - PCI_VENDOR_ID_INTEL) + if (p2sb_is_hidden()) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to unhide PCH_DEV_P2SB device !\n"); } @@ -69,8 +118,7 @@ void p2sb_hide(void) { p2sb_set_hide_bit(1); - if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != - 0xFFFF) + if (!p2sb_is_hidden()) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to hide PCH_DEV_P2SB device !\n"); } diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index b8667d04de..15b8f64891 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -5,17 +5,18 @@ #include +/* Device support at least one of enable/reset GPIO. */ struct soc_intel_common_block_pcie_rtd3_config { const char *desc; - /* GPIO used to enable device. (required) */ + /* GPIO used to enable device. */ struct acpi_gpio enable_gpio; /* Delay to be inserted after device is enabled. */ unsigned int enable_delay_ms; /* Delay to be inserted after device is disabled. */ unsigned int enable_off_delay_ms; - /* GPIO used to take device out of reset or to put it into reset. (optional) */ + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; /* Delay to be inserted after device is taken out of reset. */ unsigned int reset_delay_ms; diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 89bbbb0c45..4981205f09 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -7,6 +7,10 @@ config SOC_INTEL_DENVERTON_NS if SOC_INTEL_DENVERTON_NS +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 1 + config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 @@ -21,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 + select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -134,6 +139,9 @@ config LEGACY_UART_MODE bool "Legacy Mode" help Enable legacy UART mode + select CONSOLE_SERIAL + select DRIVERS_UART + select DRIVERS_UART_8250IO endchoice config ENABLE_HSUART @@ -153,10 +161,14 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 -config DENVERTON_NS_CAR_NEM_ENHANCED +choice + prompt "Cache-as-ram implementation" + default USE_DENVERTON_NS_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" - depends on !FSP_CAR - default y select SOC_INTEL_COMMON_BLOCK_CAR select USE_CAR_NEM_ENHANCED_V1 help @@ -167,4 +179,12 @@ config DENVERTON_NS_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_DENVERTON_NS_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + endif ## SOC_INTEL_DENVERTON_NS diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 944e8eb7c3..e7d29ff799 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include #define MWAIT_RES(state, sub_state) \ { \ @@ -268,3 +269,54 @@ void southcluster_inject_dsdt(const struct device *device) } __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + uint64_t vtbar; + unsigned long tmp = current; + + vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); + if (!vtbar) + return current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtbar); + + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Create RMRR; see "VTD PLATFORM CONFIGURATION" in FSP log */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + RMRR_USB_BASE_ADDRESS, + RMRR_USB_LIMIT_ADDRESS); + current += acpi_create_dmar_ds_pci(current, + 0, XHCI_DEV, XHCI_FUNC); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long systemagent_write_acpi_tables(const struct device *dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 7cee5be39d..1dc0830d86 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -44,6 +45,27 @@ static void dnv_configure_mca(void) of these banks are core vs package scope. For now every CPU clears every bank. */ mca_configure(); + + /* TODO install a fallback MC handler for each core in case OS does + not provide one. Is it really needed? */ + + /* Enable the machine check exception */ + write_cr4(read_cr4() | CR4_MCE); +} + +static void configure_thermal_core(void) +{ + msr_t msr; + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= THERMAL_MONITOR_ENABLE_BIT; /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); } static void denverton_core_init(struct device *cpu) @@ -55,6 +77,9 @@ static void denverton_core_init(struct device *cpu) /* Clear out pending MCEs */ dnv_configure_mca(); + /* Configure Thermal Sensors */ + configure_thermal_core(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 9bc5ed0924..86bed0024d 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -12,5 +12,8 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(const struct device *device); +unsigned long systemagent_write_acpi_tables(const struct device *dev, + unsigned long start, + struct acpi_rsdp *const rsdp); #endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 6e5f313381..fb5aafdfc8 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -24,4 +24,8 @@ #define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS #define DEFAULT_SPI_BASE 0xfed01000 +/* "VTD PLATFORM CONFIGURATION" (Set to match FSP settings) */ +#define RMRR_USB_BASE_ADDRESS 0x3e2e0000 +#define RMRR_USB_LIMIT_ADDRESS 0x3e2fffff + #endif /* _DENVERTON_NS_IOMAP_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1f64235a14..89caf44c17 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -22,6 +22,8 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) +/* IA32_MISC_ENABLE 0x1a0 */ +#define THERMAL_MONITOR_ENABLE_BIT (1 << 3) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index b6bac0b9a5..5eac5bddbe 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -143,4 +143,12 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) +/* VT-d support value to match FSP settings */ +/* "PCH IOAPIC Config" */ +#define PCH_IOAPIC_PCI_BUS 0xf0 +#define PCH_IOAPIC_PCI_SLOT 0x1f +/* "PCH HPET Config" */ +#define PCH_HPET_PCI_BUS 0 +#define PCH_HPET_PCI_SLOT 0 + #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h index 561f482f2b..0606a3ebcb 100644 --- a/src/soc/intel/denverton_ns/include/soc/systemagent.h +++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h @@ -31,6 +31,9 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define MASK_TOLUD 0xFFF00000 +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + /* SideBand B-UNIT */ #define B_UNIT 3 @@ -57,6 +60,10 @@ #define MCH_BMISC_RESDRAM \ 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */ +#define MCH_VTBAR_OFFSET 0x6c80 +#define MCH_VTBAR_ENABLE_MASK 0x1 +#define MCH_VTBAR_MASK 0x7ffffff000 + #define MCH_BAR_BIOS_RESET_CPL 0x7078 #define RST_CPL_BIT (1 << 0) #define PCODE_INIT_DONE (1 << 8) diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index daac3ebad4..114ee48d76 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -15,6 +15,7 @@ #include #include #include +#include #define _1ms 1 #define WAITING_STEP 100 @@ -325,6 +326,9 @@ static struct device_operations systemagent_ops = { .enable_resources = pci_dev_enable_resources, .init = systemagent_init, .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = systemagent_write_acpi_tables, +#endif }; /* IDs for System Agent device of Intel Denverton SoC */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f61732d332..81d37a4a5b 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -243,8 +243,8 @@ struct soc_intel_tigerlake_config { /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; - /* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */ - uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS]; + /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index cd0ada6dcc..981167a79e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -187,7 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; - params->PciePtm[i] = !config->PciePtmDisable[i]; + params->PciePtm[i] = config->PciePtm[i]; } /* Enable ClkReqDetect for enabled port */ diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index 70877d2c35..c7e969084f 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -13,3 +13,6 @@ H9HCNNNCPMMLXR-NEE,lp4x-spd-3.hex K4UBE3D4AA-MGCR,lp4x-spd-3.hex MT53E512M64D4NW-046 WT:E,lp4x-spd-1.hex MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex +H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex +H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex +MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3d3e8037db..5c7a667d2f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_P2SB select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index a10075ab04..2e50e64c25 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c -ramstage-y += memmap.c +ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 3b4b7133e4..fb4cd78dd6 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -93,20 +93,17 @@ unsigned long acpi_fill_madt(unsigned long current) /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif #if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; - ioapic_id = ioapic_ids[cur_index]; gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, ioapic_id, + current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, gsi_base); ++cur_index; @@ -117,9 +114,8 @@ unsigned long acpi_fill_madt(unsigned long current) &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (!is_iio_stack_res(ri)) continue; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; + ioapic_id = soc_get_iio_ioapicid(socket, stack); gsi_base = gsi_bases[cur_index]; uint32_t ioapic_base = ri->IoApicBase; diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3daff1372b..6beebdf925 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -10,9 +10,12 @@ #include #include #include +#include #include +#include #include #include +#include /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) @@ -63,6 +66,8 @@ static void chip_enable_dev(struct device *dev) static void chip_final(void *data) { + /* Lock SBI */ + pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); p2sb_hide(); set_bios_init_completion(); @@ -72,6 +77,7 @@ static void chip_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); + override_hpet_ioapic_bdf(); pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 68dee28a07..bcb26414d3 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -69,6 +69,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_LTDPR 0x290 /* CPU Devices */ #define CBDMA_DEV_NUM 0x04 @@ -111,23 +112,11 @@ #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00 -#define PCH_IOAPIC_BUS_NUMBER 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00 // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14 #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 578f67cda2..280bedcd77 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -63,3 +63,24 @@ int soc_get_stack_for_port(int port) else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h index 336befee60..3bdd4530ca 100644 --- a/src/soc/intel/xeon_sp/include/soc/p2sb.h +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -11,3 +11,6 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0xb0 #define P2SB_SIZE (16 * MiB) + +#define P2SBC 0xe0 +#define SBILOCK (1 << 31) diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h index 84d5e4896b..0be14ae966 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch.h +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -9,4 +9,6 @@ void pch_disable_devfn(struct device *dev); #endif +void override_hpet_ioapic_bdf(void); + #endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index fc0dee7aba..2637017c89 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -16,6 +16,7 @@ const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +uint8_t soc_get_iio_ioapicid(int socket, int stack); struct iiostack_resource { uint8_t no_of_stacks; diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index edc62cf881..cd817540b7 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -5,7 +5,10 @@ #include #include #include +#include #include +#include +#include void smm_region(uintptr_t *start, size_t *size) { @@ -41,3 +44,47 @@ void fill_postcar_frame(struct postcar_frame *pcf) if (CONFIG(TSEG_STAGE_CACHE)) postcar_enable_tseg_cache(pcf); } + +#if !defined(__SIMPLE_DEVICE__) +union dpr_register txt_get_chipset_dpr(void) +{ + const IIO_UDS *hob = get_iio_uds(); + union dpr_register dpr; + struct device *dev = VTD_DEV(0); + + dpr.raw = 0; + + if (dev == NULL) { + printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev"); + return dpr; + } + + dpr.raw = pci_read_config32(dev, VTD_LTDPR); + + /* Compare the LTDPR register on all iio stacks */ + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = + &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + if (!is_iio_stack_res(ri)) + continue; + uint8_t bus = ri->BusBase; + dev = VTD_DEV(bus); + + if (dev == NULL) { + printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus); + dpr.raw = 0; + return dpr; + } + + union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.raw != test_dpr.raw) { + printk(BIOS_ERR, "LTDPR not the same on all IIO's"); + dpr.raw = 0; + return dpr; + } + } + } + return dpr; +} +#endif diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 55c3d820ca..cb7ae40313 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "chip.h" @@ -184,15 +185,6 @@ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - uint32_t enum_id; unsigned long tmp = current; @@ -222,16 +214,16 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, // Add PCH IOAPIC if (socket == 0 && stack == CSTACK) { + union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + PCH_IOAPIC_ID, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); } // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = soc_get_iio_ioapicid(socket, stack); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, @@ -276,11 +268,12 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, //BIT 15 if (num_hpets && (num_hpets != 0x1f) && (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf(); printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); + 0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn); + current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus, + hpet_bdf.dev, hpet_bdf.fn); } } @@ -443,9 +436,15 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, if (config->vtd_support) { current = ALIGN(current, 8); dmar = (acpi_dmar_t *)current; + enum dmar_flags flags = DMAR_INTR_REMAP; + + /* SKX FSP doesn't support X2APIC, but CPX FSP does */ + if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + flags |= DMAR_X2APIC_OPT_OUT; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", flags); + acpi_create_dmar(dmar, flags, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5427952688..8de7743d94 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -5,7 +5,9 @@ #include #include #include +#include #include +#include #include #include @@ -39,6 +41,9 @@ static void soc_config_acpibase(void) reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); + + reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) @@ -48,3 +53,20 @@ void bootblock_pch_init(void) */ soc_config_acpibase(); } + +void override_hpet_ioapic_bdf(void) +{ + union p2sb_bdf ioapic_bdf = { + .bus = PCH_IOAPIC_BUS_NUMBER, + .dev = PCH_IOAPIC_DEV_NUM, + .fn = PCH_IOAPIC_FUNC_NUM, + }; + union p2sb_bdf hpet_bdf = { + .bus = HPET_BUS_NUM, + .dev = HPET_DEV_NUM, + .fn = HPET0_FUNC_NUM, + }; + + p2sb_set_ioapic_bdf(ioapic_bdf); + p2sb_set_hpet_bdf(hpet_bdf); +} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index a345c3ef6e..7fe330b37e 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ static void soc_init(void *data) { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); + override_hpet_ioapic_bdf(); } static void soc_final(void *data) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index b500c2896c..cd5d553755 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -3,6 +3,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include #include #include @@ -92,6 +93,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_LTDPR 0x290 #define PCU_CR1_C2C3TT_REG 0xdc #define PCU_CR1_PCIE_ILTR_OVRD 0xfc @@ -161,17 +163,5 @@ // ========== IOAPIC Definitions for DMAR/ACPI ======== #define PCH_IOAPIC_ID 0x08 -#define PC00_IOAPIC_ID 0x09 -#define PC01_IOAPIC_ID 0x0A -#define PC02_IOAPIC_ID 0x0B -#define PC03_IOAPIC_ID 0x0C -#define PC04_IOAPIC_ID 0x0D -#define PC05_IOAPIC_ID 0x0E -#define PC06_IOAPIC_ID 0x0F -#define PC07_IOAPIC_ID 0x10 -#define PC08_IOAPIC_ID 0x11 -#define PC09_IOAPIC_ID 0x12 -#define PC10_IOAPIC_ID 0x13 -#define PC11_IOAPIC_ID 0x14 #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7d95ae8600..b903249e1d 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -148,3 +148,24 @@ int soc_get_stack_for_port(int port) else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/common/auxadc.c similarity index 86% rename from src/soc/mediatek/mt8183/auxadc.c rename to src/soc/mediatek/common/auxadc.c index 19c994872f..6dbf12bbe9 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/common/auxadc.c @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include +#include #include #include #include -#include #include static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; @@ -36,9 +35,10 @@ static void mt_auxadc_update_cali(void) cali_oe = cali_oe_a - 512; } } + static uint32_t auxadc_get_rawdata(int channel) { - setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); + setbits32(&mtk_infracfg->module_sw_cg_1_clr, 1 << 10); assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); clrbits32(&mtk_auxadc->con1, 1 << channel); @@ -50,12 +50,12 @@ static uint32_t auxadc_get_rawdata(int channel) uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; - setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); + setbits32(&mtk_infracfg->module_sw_cg_1_set, 1 << 10); return value; } -int auxadc_get_voltage(unsigned int channel) +unsigned int auxadc_get_voltage_uv(unsigned int channel) { uint32_t raw_value; assert(channel < 16); @@ -67,7 +67,6 @@ int auxadc_get_voltage(unsigned int channel) /* 1.5V in 4096 steps */ raw_value = auxadc_get_rawdata(channel); - raw_value = raw_value - cali_oe; - return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge)); + return (unsigned int)((int64_t)raw_value * 1500000 / (4096 + cali_ge)); } diff --git a/src/soc/mediatek/common/include/soc/auxadc_common.h b/src/soc/mediatek/common/include/soc/auxadc_common.h new file mode 100644 index 0000000000..de2408fef1 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/auxadc_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_COMMON_H +#define _MTK_ADC_COMMON_H + +/* Return voltage in uVolt */ +unsigned int auxadc_get_voltage_uv(unsigned int channel); +#endif diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 258d5503f1..0cd0f1e8b7 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -10,10 +10,16 @@ enum mtk_regulator { MTK_REGULATOR_VDD2, MTK_REGULATOR_VDDQ, MTK_REGULATOR_VMDDR, + MTK_REGULATOR_VCORE, + MTK_REGULATOR_VCC, + MTK_REGULATOR_VCCQ, }; void mainboard_set_regulator_vol(enum mtk_regulator regulator, uint32_t voltage_uv); uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator); +int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable); +uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator); + #endif /* SOC_MEDIATEK_COMMON_REGULATOR_H */ diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b0dd48f7a4..43893c363d 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y) -bootblock-y += auxadc.c bootblock-y += bootblock.c +bootblock-y += ../common/auxadc.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -15,7 +15,7 @@ decompressor-y += decompressor.c decompressor-y += ../common/mmu_operations.c decompressor-y += ../common/timer.c -verstage-y += auxadc.c +verstage-y += ../common/auxadc.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += mt8183.c @@ -24,7 +24,7 @@ verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c -romstage-y += auxadc.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_init_setting.c romstage-y += dramc_param.c @@ -44,8 +44,8 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c -ramstage-y += auxadc.c ramstage-y += emi.c +ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8183/include/soc/auxadc.h b/src/soc/mediatek/mt8183/include/soc/auxadc.h index 18350d63f0..0e07de073c 100644 --- a/src/soc/mediatek/mt8183/include/soc/auxadc.h +++ b/src/soc/mediatek/mt8183/include/soc/auxadc.h @@ -3,6 +3,8 @@ #ifndef _MTK_ADC_H #define _MTK_ADC_H +#include +#include #include typedef struct mtk_auxadc_regs { @@ -16,6 +18,6 @@ typedef struct mtk_auxadc_regs { uint32_t misc; } mtk_auxadc_regs; -/* Return voltage in uVolt */ -int auxadc_get_voltage(unsigned int channel); +static struct mt8183_infracfg_regs *const mtk_infracfg = mt8183_infracfg; + #endif diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 13b5b21763..421968d85a 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -9,23 +10,31 @@ bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += mt6315.c +bootblock-y += mt6359p.c +verstage-y += ../common/auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c +romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +romstage-y += mt6359p.c +ramstage-y += ../common/auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 8dffe5671b..7987b1cf8e 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,7 +2,10 @@ #include #include +#include +#include #include +#include #include void bootblock_soc_init(void) @@ -10,4 +13,7 @@ void bootblock_soc_init(void) mtk_mmu_init(); mtk_wdt_init(); mt_pll_init(); + mtk_pmif_init(); + mt6359p_init(); + mt6315_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd5364a3..12094ffe5d 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -21,7 +21,11 @@ enum { GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, - PWRAP_BASE = IO_PHYS + 0x0000D000, + PMIF_SPI_BASE = IO_PHYS + 0x00026000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + PMICSPI_MST_BASE = IO_PHYS + 0x00028000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, + AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, @@ -33,6 +37,7 @@ enum { SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h new file mode 100644 index 0000000000..3289a22ccf --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include +#include +#include + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8192_infracfg_regs *const mtk_infracfg = mt8192_infracfg; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h new file mode 100644 index 0000000000..f0f3405a5a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include +#include + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index df9d376f27..c016d5faa7 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -21,11 +26,16 @@ SECTIONS TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) - TIMESTAMP(0x00113c00, 1K) - STACK(0x00114000, 16K) - TTB(0x00118000, 28K) - DMA_COHERENT(0x0011f000, 4K) + PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4) + TIMESTAMP(0x00108c00, 1K) + STACK(0x00109000, 16K) + TTB(0x0010d000, 28K) + DMA_COHERENT(0x00114000, 4K) + /* + * MCUPM exchanges data with kernel driver using SRAM 0x00115000 ~ 0x0011ffff. + * The address is hardcoded in MCUPM image and is unlikely to change. + */ + REGION(mcufw_reserved, 0x00115000, 44K, 4K) SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) @@ -36,8 +46,9 @@ SECTIONS SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 256K) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/mt6315.h b/src/soc/mediatek/mt8192/include/soc/mt6315.h new file mode 100644 index 0000000000..4d179bed68 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6315.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6315_H__ +#define __SOC_MEDIATEK_MT6315_H__ + +#include +#include + +struct mt6315_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6315_CPU = SPMI_SLAVE_6, + MT6315_GPU = SPMI_SLAVE_7, + MT6315_MAX, +}; + +enum { + MT6315_BUCK_1 = 0, + MT6315_BUCK_2, + MT6315_BUCK_3, + MT6315_BUCK_4, + MT6315_BUCK_max, +}; + +enum { + MT6315_BUCK_TOP_ELR0 = 0x1449, + MT6315_BUCK_TOP_ELR3 = 0x144d, + MT6315_BUCK_VBUCK1_DBG0 = 0x1499, + MT6315_BUCK_VBUCK1_DBG3 = 0x1599, +}; + +void mt6315_init(void); +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv); +u32 mt6315_buck_get_voltage(u32 slvid, u32 buck_id); +#endif /* __SOC_MEDIATEK_MT6315_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h new file mode 100644 index 0000000000..b90e0f55ed --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6359P_H__ +#define __SOC_MEDIATEK_MT6359P_H__ + +#include + +enum { + PMIC_HWCID = 0x0008, + PMIC_SWCID = 0x000a, + PMIC_TOP_RST_MISC_SET = 0x014c, + PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_PWRHOLD = 0x0a08, + PMIC_VGPU11_DBG0 = 0x15a6, + PMIC_VGPU11_ELR0 = 0x15b4, + PMIC_VS2_VOTER = 0x18aa, + PMIC_VS2_VOTER_CFG = 0x18b0, + PMIC_VS2_ELR0 = 0x18b4, + PMIC_VSRAM_PROC1_ELR = 0x1b44, + PMIC_VSRAM_PROC2_ELR = 0x1b46, + PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90, + PMIC_VSRAM_PROC2_VOSEL1 = 0x1eb0, + PMIC_VM18_ANA_CON0 = 0x2020, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6359P_GPU11 = 0, + MT6359P_SRAM_PROC1, + MT6359P_SRAM_PROC2, + MT6359P_MAX, +}; + +#define VM18_VOL_REG_SHIFT 8 +#define VM18_VOL_OFFSET 600 + +void mt6359p_init(void); +void mt6359p_romstage_init(void); +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); +u32 mt6359p_buck_get_voltage(u32 buck_id); +void mt6359p_set_vm18_voltage(u32 vm18_uv); +u32 mt6359p_get_vm18_voltage(void); +#endif /* __SOC_MEDIATEK_MT6359P_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/mt6360.h b/src/soc/mediatek/mt8192/include/soc/mt6360.h new file mode 100644 index 0000000000..a6ee76c08b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6360.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6360_H__ +#define __SOC_MEDIATEK_MT6360_H__ + +enum mt6360_regulator_id { + MT6360_LDO3 = 0, + MT6360_LDO5, + MT6360_LDO6, + MT6360_LDO7, + MT6360_BUCK1, + MT6360_BUCK2, + MT6360_REGULATOR_COUNT, +}; + +#endif /* __SOC_MEDIATEK_MT6360_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index d5a9cf9a3e..09c4c47118 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -178,7 +178,11 @@ struct mtk_apmixed_regs { u32 mfgpll_con2; u32 mfgpll_con3; u32 ap_pllgp1_con2; - u32 reserved2[33]; + u32 reserved2[13]; + u32 ulposc1_con0; + u32 ulposc1_con1; + u32 ulposc1_con2; + u32 reserved3[17]; u32 ap_pllgp2_con0; /* 0x0300 */ u32 ap_pllgp2_con1; u32 univpll_con0; diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h new file mode 100644 index 0000000000..fe3def020a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT8192_SOC_PMIF_H__ +#define __MT8192_SOC_PMIF_H__ + +#include + +enum { + PMIF_CMD_REG_0, + PMIF_CMD_REG, + PMIF_CMD_EXT_REG, + PMIF_CMD_EXT_REG_LONG, +}; + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[5]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[502]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1DC); +check_member(mtk_pmif_regs, crc_ctrl, 0x398); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B4); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E0); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x400); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x40C); +check_member(mtk_pmif_regs, irq_event_en_0, 0x418); +check_member(mtk_pmif_regs, swinf_0_acc, 0xC00); + +#define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0xC80) +#define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0xC80) + +struct chan_regs { + u32 ch_send; + u32 wdata; + u32 reserved12[3]; + u32 rdata; + u32 reserved13[3]; + u32 ch_rdy; + u32 ch_sta; +}; + +struct pmif { + struct mtk_pmif_regs *mtk_pmif; + struct chan_regs *ch; + u32 swinf_no; + u32 mstid; + u32 pmifid; + void (*read)(struct pmif *arb, u32 slvid, u32 reg, u32 *data); + void (*write)(struct pmif *arb, u32 slvid, u32 reg, u32 data); + u32 (*read_field)(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift); + void (*write_field)(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift); + int (*is_pmif_init_done)(struct pmif *arb); +}; + +enum { + PMIF_SPI, + PMIF_SPMI, +}; + +enum { + E_IO = 1, /* I/O error */ + E_BUSY, /* Device or resource busy */ + E_NODEV, /* No such device */ + E_INVAL, /* Invalid argument */ + E_OPNOTSUPP, /* Operation not supported on transport endpoint */ + E_TIMEOUT, /* Wait for idle time out */ + E_READ_TEST_FAIL, /* SPI read fail */ + E_SPI_INIT_RESET_SPI, /* Reset SPI fail */ + E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ +}; + +extern struct pmif *get_pmif_controller(int inf, int mstid); +extern int mtk_pmif_init(void); +#endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h new file mode 100644 index 0000000000..426aa3bf28 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ + +#include +#include + +struct mt8192_pmicspi_mst_regs { + u32 reserved1[4]; + u32 other_busy_sta_0; + u32 wrap_en; + u32 reserved2[2]; + u32 man_en; + u32 man_acc; + u32 reserved3[3]; + u32 mux_sel; + u32 reserved4[3]; + u32 dio_en; + u32 rddmy; + u32 cslext_write; + u32 cslext_read; + u32 cshext_write; + u32 cshext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 si_sampling_ctrl; +}; + +check_member(mt8192_pmicspi_mst_regs, other_busy_sta_0, 0x10); +check_member(mt8192_pmicspi_mst_regs, man_en, 0x20); +check_member(mt8192_pmicspi_mst_regs, mux_sel, 0x34); +check_member(mt8192_pmicspi_mst_regs, dio_en, 0x44); + +static struct mt8192_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE; + +struct mt8192_iocfg_lm_regs { + u32 reserved[4]; + u32 drv_cfg1; +}; +check_member(mt8192_iocfg_lm_regs, drv_cfg1, 0x10); + +static struct mt8192_iocfg_lm_regs * const mtk_iocfg_lm = (void *)IOCFG_LM_BASE; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0032, + PMIC_DRV_CON1 = PMIC_BASE + 0x003a, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0042, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040c, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040e, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0424, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0426, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044a, + PMIC_INT_STA = PMIC_BASE + 0x0452, + PMIC_AUXADC_ADC7 = PMIC_BASE + 0x1096, + PMIC_AUXADC_ADC10 = PMIC_BASE + 0x109c, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, +}; + +#define PMIF_SPI_HW_INF 0x307F +#define PMIF_SPI_MD BIT(8) +#define PMIF_SPI_AP_SECURE BIT(9) +#define PMIF_SPI_AP BIT(10) +#define PMIF_SPI_STAUPD BIT(14) +#define PMIF_SPI_TSX_HW BIT(19) +#define PMIF_SPI_DCXO_HW BIT(20) + +#define DEFAULT_SLVID 0 + +#define PMIF_CMD_STA BIT(2) +#define SPIMST_STA BIT(9) + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO, + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x1, + SLV_IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = SLV_IO_4_MA << SPI_CLK_SHIFT | SLV_IO_4_MA << SPI_CSN_SHIFT | + SLV_IO_4_MA << SPI_MOSI_SHIFT | SLV_IO_4_MA << SPI_MISO_SHIFT, +}; + +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a, +}; + +enum { + DUMMY_READ_CYCLES = 0x8, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING, +}; +extern int pmif_spi_init(struct pmif *arb); +#endif /* __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h new file mode 100644 index 0000000000..d89a072123 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SPMI_H__ +#define __PMIF_SPMI_H__ + +#include + +#define DEFAULT_VALUE_READ_TEST (0x5a) +#define DEFAULT_VALUE_WRITE_TEST (0xa5) + +/* indicate which number SW channel start, by project */ +#define PMIF_SPMI_SW_CHAN BIT(6) +#define PMIF_SPMI_INF 0x2F7 + +struct mtk_rgu_regs { + u32 reserved[36]; + u32 wdt_swsysrst2; +}; +check_member(mtk_rgu_regs, wdt_swsysrst2, 0x90); + +struct mtk_iocfg_bm_regs { + u32 reserved[8]; + u32 drv_cfg2; +}; +check_member(mtk_iocfg_bm_regs, drv_cfg2, 0x20); + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 reserved[263]; + u32 ulposc_con; +}; +check_member(mtk_spm_regs, ulposc_con, 0x420); + +struct mtk_spmi_mst_reg { + u32 op_st_ctrl; + u32 grp_id_en; + u32 op_st_sta; + u32 mst_sampl; + u32 mst_req_en; + u32 reserved1[11]; + u32 rec_ctrl; + u32 rec0; + u32 rec1; + u32 rec2; + u32 rec3; + u32 rec4; + u32 reserved2[41]; + u32 mst_dbg; +}; + +check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40); +check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc); + +#define mtk_rug ((struct mtk_rgu_regs *)RGU_BASE) +#define mtk_iocfg_bm ((struct mtk_iocfg_bm_regs *)IOCFG_BM_BASE) +#define mtk_spm ((struct mtk_spm_regs *)SPM_BASE) +#define mtk_spmi_mst ((struct mtk_spmi_mst_reg *)SPMI_MST_BASE) + +struct cali { + unsigned int dly; + unsigned int pol; +}; + +enum { + SPMI_CK_NO_DLY = 0, + SPMI_CK_DLY_1T, +}; + +enum { + SPMI_CK_POL_NEG = 0, + SPMI_CK_POL_POS, +}; + +enum spmi_regs { + SPMI_OP_ST_CTRL, + SPMI_GRP_ID_EN, + SPMI_OP_ST_STA, + SPMI_MST_SAMPL, + SPMI_MST_REQ_EN, + SPMI_REC_CTRL, + SPMI_REC0, + SPMI_REC1, + SPMI_REC2, + SPMI_REC3, + SPMI_REC4, + SPMI_MST_DBG +}; + +/* MT6315 registers */ +enum { + MT6315_BASE = 0x0, + MT6315_READ_TEST = MT6315_BASE + 0x9, + MT6315_READ_TEST_1 = MT6315_BASE + 0xb, +}; + +#define MT6315_DEFAULT_VALUE_READ 0x15 + +extern int pmif_spmi_init(struct pmif *arb); +#endif /*__PMIF_SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_sw.h b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h new file mode 100644 index 0000000000..fb4cbc967e --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SW_H__ +#define __PMIF_SW_H__ + +/* Read/write byte limitation, by project */ +/* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ +#define PMIF_BYTECNT_MAX 1 + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE 0x00 +#define SWINF_FSM_REQ 0x02 +#define SWINF_FSM_WFDLE 0x04 +#define SWINF_FSM_WFVLDCLR 0x06 +#define SWINF_INIT_DONE 0x01 + +#define FREQ_METER_ABIST_AD_OSC_CK 37 +#define GET_SWINF_0_FSM(x) (((x) >> 1) & 0x7) + +struct pmif_mpu { + unsigned int rgn_slvid; + unsigned short rgn_s_addr; + unsigned short rgn_e_addr; + unsigned int rgn_domain_per; +}; + +enum { + PMIF_READ_US = 1000, + PMIF_WAIT_IDLE_US = 1000, +}; + +enum { + FREQ_260MHZ = 260, +}; + +/* calibation tolerance rate, unit: 0.1% */ +enum { + CAL_TOL_RATE = 40, + CAL_MAX_VAL = 0x7F, +}; + +extern int pmif_clk_init(void); +#endif /*__PMIF_SW_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/spmi.h b/src/soc/mediatek/mt8192/include/soc/spmi.h new file mode 100644 index 0000000000..0d44198f82 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spmi.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SPMI_H__ +#define __SPMI_H__ + +enum spmi_master { + SPMI_MASTER_0, + SPMI_MASTER_1, + SPMI_MASTER_2, + SPMI_MASTER_3, +}; + +enum spmi_slave { + SPMI_SLAVE_0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15, + SPMI_SLAVE_MAX, +}; + +enum slv_type { + BUCK_CPU, + BUCK_GPU, + SLV_TYPE_MAX, +}; + +enum slv_type_id { + BUCK_CPU_ID, + BUCK_GPU_ID, + SLV_TYPE_ID_MAX, +}; + +struct spmi_device { + u32 slvid; + enum slv_type type; + enum slv_type_id type_id; +}; +#endif /*__SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h new file mode 100644 index 0000000000..a7feee7ea0 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#include + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620eb82..e3bc62282d 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include #include #include +#include DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void) MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c new file mode 100644 index 0000000000..9752e3dfcb --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6315.c @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static struct pmif *pmif_arb = NULL; + +static const struct mt6315_setting init_setting_cpu[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* clear boot status */ + {0x12A, 0x3, 0xFF, 0}, + {0xD, 1, 0x1, 0}, + {0xD, 0, 0x1, 0}, + {0x1416, 0xF, 0xF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x7, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x1, 0x1F, 0}, + {0x9A1, 0x1, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x1, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x2, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x2, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x2, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x20, 0x70, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0x80, 0xC1, 0}, + {0x169E, 0xF8, 0xF8, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xDB, 0xFF, 0}, + {0x16A3, 0xA1, 0xFF, 0}, + {0x16A4, 0x1, 0xF, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static const struct mt6315_setting init_setting_gpu[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3a2, 0x2A, 0xFF, 0}, + {0x3a1, 0x7C, 0xFF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x2F, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0xB, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x4, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x4, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x4, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0x7F, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x13, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */ + {0x1440, 0x0, 0x4, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static void mt6315_read(u32 slvid, u32 reg, u32 *data) +{ + pmif_arb->read(pmif_arb, slvid, reg, data); +} + +static void mt6315_write(u32 slvid, u32 reg, u32 data) +{ + pmif_arb->write(pmif_arb, slvid, reg, data); +} + +static void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) +{ + pmif_arb->write_field(pmif_arb, 0, reg, val, mask, shift); +} + +static void mt6315_wdt_enable(u32 slvid) +{ + mt6315_write(slvid, 0x3A9, 0x63); + mt6315_write(slvid, 0x3A8, 0x15); + mt6315_write(slvid, 0x127, 0x2); + mt6315_write(slvid, 0x127, 0x1); + mt6315_write(slvid, 0x127, 0x8); + udelay(50); + mt6315_write(slvid, 0x128, 0x8); + mt6315_write(slvid, 0x3A9, 0); + mt6315_write(slvid, 0x3A8, 0); +} + +static void mt6315_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++) + mt6315_write_field(MT6315_CPU, + init_setting_cpu[i].addr, init_setting_cpu[i].val, + init_setting_cpu[i].mask, init_setting_cpu[i].shift); + + for (int i = 0; i < ARRAY_SIZE(init_setting_gpu); i++) + mt6315_write_field(MT6315_GPU, + init_setting_gpu[i].addr, init_setting_gpu[i].val, + init_setting_gpu[i].mask, init_setting_gpu[i].shift); +} + +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv) +{ + unsigned int vol_reg, vol_val; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_TOP_ELR0; + break; + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_TOP_ELR3; + break; + default: + die("ERROR: Unknown buck_id %u", buck_id); + return; + }; + + vol_val = buck_uv / 6250; + mt6315_write(slvid, vol_reg, vol_val); +} + +u32 mt6315_buck_get_voltage(u32 slvid, u32 buck_id) +{ + u32 vol_reg, vol; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_VBUCK1_DBG0; + break; + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_VBUCK1_DBG3; + break; + default: + die("ERROR: Unknown buck_id %u", buck_id); + return 0; + }; + + mt6315_read(slvid, vol_reg, &vol); + return vol * 6250; +} + +static void init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + if (!pmif_arb) + die("ERROR: No spmi device"); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi"); +} + +void mt6315_init(void) +{ + init_pmif_arb(); + mt6315_wdt_enable(MT6315_CPU); + mt6315_wdt_enable(MT6315_GPU); + mt6315_init_setting(); +} diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c new file mode 100644 index 0000000000..1646e534e4 --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -0,0 +1,448 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const struct pmic_setting init_setting[] = { + {0x20, 0xA, 0xA, 0}, + {0x24, 0x1F00, 0x1F00, 0}, + {0x30, 0x1, 0x1, 0}, + {0x32, 0x1, 0x1, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x10, 0x10, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x14A, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x1B2, 0x3, 0x3, 0}, + {0x3B0, 0x0, 0x300, 0}, + {0x790, 0x3, 0x3, 0}, + {0x7A6, 0xF800, 0xFC00, 0}, + {0x7A8, 0x0, 0x280, 0}, + {0x98A, 0x80, 0x80, 0}, + {0x992, 0xF00, 0xF00, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA0C, 0x300, 0x300, 0}, + {0xA10, 0x0, 0x4000, 0}, + {0xA12, 0x1E0, 0x1E0, 0}, + {0xA24, 0xFFFF, 0xFFFF, 0}, + {0xA26, 0xFFE0, 0xFFE0, 0}, + {0xA2C, 0xC0DF, 0xC0DF, 0}, + {0xA2E, 0xEBE0, 0xEBE0, 0}, + {0xA34, 0x8000, 0x8000, 0}, + {0xA3C, 0x1C00, 0x1F00, 0}, + {0xA3E, 0x341, 0x7FFF, 0}, + {0xA40, 0x1042, 0x7FFF, 0}, + {0xA42, 0xC05, 0x7FFF, 0}, + {0xA44, 0x20E5, 0x7FFF, 0}, + {0xA46, 0x2652, 0x7FFF, 0}, + {0xA48, 0x716A, 0x7FFF, 0}, + {0xA4A, 0x62EC, 0x7FFF, 0}, + {0xA4C, 0x5676, 0x7FFF, 0}, + {0xA4E, 0x6F34, 0x7FFF, 0}, + {0xA50, 0xC0, 0x7FFF, 0}, + {0xA9C, 0x4000, 0x4000, 0}, + {0xA9E, 0x2E11, 0xFF11, 0}, + {0xF8C, 0x115, 0x115, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x1198, 0x13, 0x3FF, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11D4, 0x0, 0x2, 0}, + {0x1212, 0x0, 0x2, 0}, + {0x1224, 0x0, 0x2, 0}, + {0x1238, 0x0, 0x2, 0}, + {0x124A, 0x0, 0x2, 0}, + {0x125C, 0x0, 0x2, 0}, + {0x125E, 0x0, 0x8000, 0}, + {0x1260, 0x1, 0xFFF, 0}, + {0x1262, 0x4, 0x4, 0}, + {0x1412, 0x8, 0x8, 0}, + {0x148E, 0x18, 0x7F, 0}, + {0x1492, 0x505, 0x7F7F, 0}, + {0x1514, 0x2, 0x2, 0}, + {0x1520, 0x0, 0x2, 0}, + {0x152C, 0x7F, 0x7F, 0}, + {0x158E, 0x18, 0x7F, 0}, + {0x1592, 0xC00, 0x7F00, 0}, + {0x160E, 0x18, 0x7F, 0}, + {0x1694, 0x2, 0x2, 0}, + {0x16A0, 0x0, 0x2, 0}, + {0x16AE, 0x50, 0x7F, 0}, + {0x170E, 0x18, 0x7F, 0}, + {0x178E, 0x18, 0x7F, 0}, + {0x198A, 0x5004, 0x502C, 0}, + {0x198C, 0x11, 0x3F, 0}, + {0x198E, 0x1E0, 0x1E0, 0}, + {0x1990, 0xFD, 0xFF, 0}, + {0x1994, 0x10, 0x38, 0}, + {0x1996, 0x2004, 0xA02C, 0}, + {0x1998, 0x11, 0x3F, 0}, + {0x199A, 0xFB78, 0xFF78, 0}, + {0x199E, 0x2, 0x7, 0}, + {0x19A0, 0x1050, 0x10F1, 0}, + {0x19A2, 0x18, 0x38, 0}, + {0x19A4, 0xF, 0xF, 0}, + {0x19A6, 0x30, 0xFF, 0}, + {0x19AC, 0x4200, 0x4680, 0}, + {0x19AE, 0x6E, 0x7E, 0}, + {0x19B0, 0x3C00, 0x3C00, 0}, + {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x1A08, 0x4200, 0x4680, 0}, + {0x1A0A, 0x6E, 0x7E, 0}, + {0x1A0C, 0x3C00, 0x3C00, 0}, + {0x1A10, 0x20FD, 0xFFFF, 0}, + {0x1A14, 0x4208, 0x4698, 0}, + {0x1A16, 0x46, 0x7E, 0}, + {0x1A18, 0x3C00, 0x3C00, 0}, + {0x1A1C, 0x30FF, 0xFFFF, 0}, + {0x1A1E, 0x0, 0x200, 0}, + {0x1A20, 0x4208, 0x4698, 0}, + {0x1A22, 0x4A, 0x7E, 0}, + {0x1A24, 0x3C00, 0x3C00, 0}, + {0x1A28, 0x3000, 0xFF00, 0}, + {0x1A2C, 0x20, 0x74, 0}, + {0x1A2E, 0x1E, 0x1E, 0}, + {0x1A30, 0x42, 0xFF, 0}, + {0x1A32, 0x480, 0x7E0, 0}, + {0x1A34, 0x20, 0x74, 0}, + {0x1A36, 0x1E, 0x1E, 0}, + {0x1A38, 0x42, 0xFF, 0}, + {0x1A3A, 0x480, 0x7E0, 0}, + {0x1A3C, 0x14C, 0x3CC, 0}, + {0x1A3E, 0x23C, 0x3FC, 0}, + {0x1A40, 0xC400, 0xFF00, 0}, + {0x1A42, 0x80, 0xFF, 0}, + {0x1A44, 0x702C, 0xFF2C, 0}, + {0x1B0E, 0xF, 0xF, 0}, + {0x1B10, 0x1, 0x1, 0}, + {0x1B14, 0xFFFF, 0xFFFF, 0}, + {0x1B1A, 0x3FFF, 0x3FFF, 0}, + {0x1B32, 0x8, 0x8, 0}, + {0x1B8A, 0x30, 0x8030, 0}, + {0x1B9C, 0x10, 0x8010, 0}, + {0x1BA0, 0x4000, 0x4000, 0}, + {0x1BAE, 0x1410, 0x9C10, 0}, + {0x1BB2, 0x2, 0x2, 0}, + {0x1BC0, 0x10, 0x8010, 0}, + {0x1BD2, 0x13, 0x8013, 0}, + {0x1BE4, 0x10, 0x8010, 0}, + {0x1C0A, 0x10, 0x8010, 0}, + {0x1C1E, 0x10, 0x8010, 0}, + {0x1C30, 0x10, 0x8010, 0}, + {0x1C42, 0x10, 0x8010, 0}, + {0x1C54, 0x32, 0x8033, 0}, + {0x1C66, 0x10, 0x8010, 0}, + {0x1C8A, 0x10, 0x8010, 0}, + {0x1C8E, 0x4000, 0x4000, 0}, + {0x1C9C, 0x10, 0x8010, 0}, + {0x1CAE, 0x10, 0x8010, 0}, + {0x1CC0, 0x10, 0x8010, 0}, + {0x1CD2, 0x33, 0x8033, 0}, + {0x1CE4, 0x33, 0x8033, 0}, + {0x1D0A, 0x10, 0x8010, 0}, + {0x1D1E, 0x10, 0x8010, 0}, + {0x1D22, 0x4000, 0x4000, 0}, + {0x1D30, 0x10, 0x8010, 0}, + {0x1D34, 0x4000, 0x4000, 0}, + {0x1D42, 0x30, 0x8030, 0}, + {0x1D46, 0x4000, 0x4000, 0}, + {0x1D54, 0x30, 0x8030, 0}, + {0x1D66, 0x32, 0x8033, 0}, + {0x1D8A, 0x10, 0x8010, 0}, + {0x1D9C, 0x10, 0x8010, 0}, + {0x1E8A, 0x10, 0x8010, 0}, + {0x1E92, 0xC12, 0x7F7F, 0}, + {0x1EAA, 0x10, 0x8010, 0}, + {0x1EB2, 0xC1F, 0x7F7F, 0}, + {0x1F0A, 0x10, 0x8010, 0}, + {0x1F12, 0xC1F, 0x7F7F, 0}, + {0x1F30, 0x10, 0x8010, 0}, + {0x1F38, 0xF1F, 0x7F7F, 0}, + {0x200A, 0x8, 0xC, 0}, + {0x202C, 0x8, 0xC, 0}, + {0x208C, 0x100, 0xF00, 0}, + {0x209C, 0x80, 0x1E0, 0}, +}; + +static const struct pmic_setting lp_setting[] = { + /* Suspend */ + {0x1520, 0x0, 0x1, 0x1}, + {0x1514, 0x1, 0x1, 0x1}, + {0x151a, 0x0, 0x1, 0x1}, + {0x14a0, 0x1, 0x1, 0x1}, + {0x1494, 0x1, 0x1, 0x1}, + {0x149a, 0x1, 0x1, 0x1}, + {0x1714, 0x1, 0x1, 0xf}, + {0x1794, 0x1, 0x1, 0xf}, + {0x15a0, 0x1, 0x1, 0x0}, + {0x1594, 0x1, 0x1, 0x0}, + {0x159a, 0x1, 0x1, 0x0}, + {0x1614, 0x1, 0x1, 0xf}, + {0x16a0, 0x0, 0x1, 0x1}, + {0x1694, 0x1, 0x1, 0x1}, + {0x169a, 0x0, 0x1, 0x1}, + {0x1820, 0x1, 0x1, 0x0}, + {0x1814, 0x1, 0x1, 0x0}, + {0x181a, 0x1, 0x1, 0x0}, + {0x18a0, 0x1, 0x1, 0x0}, + {0x1894, 0x1, 0x1, 0x0}, + {0x189a, 0x1, 0x1, 0x0}, + {0x1e96, 0x1, 0x1, 0xf}, + {0x1eb6, 0x1, 0x1, 0xf}, + {0x1f16, 0x1, 0x1, 0xf}, + {0x1f3c, 0x1, 0x1, 0xf}, + {0x1c58, 0x1, 0x1, 0xf}, + {0x1d8e, 0x1, 0x1, 0xf}, + {0x1c34, 0x1, 0x1, 0xf}, + {0x1c22, 0x1, 0x1, 0xf}, + {0x1bae, 0x0, 0x1, 0xb}, + {0x1bb2, 0x1, 0x1, 0x1}, + {0x1bb8, 0x0, 0x1, 0x1}, + {0x1cb2, 0x1, 0x1, 0xf}, + {0x1bd6, 0x1, 0x1, 0xf}, + {0x1bc0, 0x1, 0x1, 0xa}, + {0x1bc4, 0x1, 0x1, 0x0}, + {0x1bca, 0x1, 0x1, 0x0}, + {0x1d22, 0x1, 0x1, 0xe}, + {0x1d28, 0x0, 0x1, 0xe}, + {0x1c66, 0x1, 0x1, 0xa}, + {0x1c6a, 0x1, 0x1, 0x0}, + {0x1c70, 0x1, 0x1, 0x0}, + {0x1c42, 0x1, 0x1, 0xb}, + {0x1c46, 0x1, 0x1, 0x1}, + {0x1c4c, 0x1, 0x1, 0x1}, + {0x1d34, 0x1, 0x1, 0xe}, + {0x1d3a, 0x0, 0x1, 0xe}, + {0x1b8a, 0x0, 0x1, 0xb}, + {0x1b8e, 0x1, 0x1, 0x1}, + {0x1b94, 0x0, 0x1, 0x1}, + {0x1d42, 0x1, 0x1, 0xa}, + {0x1d46, 0x1, 0x1, 0x0}, + {0x1d4c, 0x0, 0x1, 0x0}, + {0x1ca0, 0x1, 0x1, 0xf}, + {0x1c8a, 0x1, 0x1, 0xa}, + {0x1c8e, 0x1, 0x1, 0x0}, + {0x1c94, 0x1, 0x1, 0x0}, + {0x1b9c, 0x1, 0x1, 0xa}, + {0x1ba0, 0x1, 0x1, 0x0}, + {0x1ba6, 0x1, 0x1, 0x0}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xa}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1cc4, 0x1, 0x1, 0xf}, + {0x1d6a, 0x1, 0x1, 0xf}, + {0x1cd6, 0x1, 0x1, 0xf}, + {0x1ce8, 0x1, 0x1, 0xf}, + {0x1da0, 0x1, 0x1, 0xf}, + {0x1d58, 0x1, 0x1, 0xf}, + + /* Deepidle */ + {0x15a0, 0x1, 0x1, 0x2}, + {0x1594, 0x1, 0x1, 0x2}, + {0x159a, 0x1, 0x1, 0x2}, + {0x1820, 0x1, 0x1, 0x2}, + {0x1814, 0x1, 0x1, 0x2}, + {0x181a, 0x1, 0x1, 0x2}, + {0x18a0, 0x1, 0x1, 0x2}, + {0x1894, 0x1, 0x1, 0x2}, + {0x189a, 0x1, 0x1, 0x2}, + {0x1bc0, 0x1, 0x1, 0xc}, + {0x1bc4, 0x1, 0x1, 0x2}, + {0x1bca, 0x1, 0x1, 0x2}, + {0x1c66, 0x1, 0x1, 0xc}, + {0x1c6a, 0x1, 0x1, 0x2}, + {0x1c70, 0x1, 0x1, 0x2}, + {0x1d42, 0x1, 0x1, 0xc}, + {0x1d46, 0x1, 0x1, 0x2}, + {0x1d4c, 0x0, 0x1, 0x2}, + {0x1c8a, 0x1, 0x1, 0xc}, + {0x1c8e, 0x1, 0x1, 0x2}, + {0x1c94, 0x1, 0x1, 0x2}, + {0x1b9c, 0x1, 0x1, 0xc}, + {0x1ba0, 0x1, 0x1, 0x2}, + {0x1ba6, 0x1, 0x1, 0x2}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xc}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, +}; + +static struct pmif *pmif_arb = NULL; +static void mt6359p_write(u32 reg, u32 data) +{ + pmif_arb->write(pmif_arb, 0, reg, data); +} + +static u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift) +{ + return pmif_arb->read_field(pmif_arb, 0, reg, mask, shift); +} + +static void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + pmif_arb->write_field(pmif_arb, 0, reg, val, mask, shift); +} + +static void pmic_set_power_hold(void) +{ + mt6359p_write_field(PMIC_PWRHOLD, 0x1, 0x1, 0); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x20, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6359p_write_field(PMIC_TOP_RST_MISC_CLR, 0x02, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); +} + +static void pmic_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6359p_write_field(init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +static void pmic_lp_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(lp_setting); i++) + mt6359p_write_field(lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +static void pmic_wk_vs2_voter_setting(void) +{ + /* + * 1. Set VS2_VOTER_VOSEL = 1.35V + * 2. Clear VS2_VOTER + * 3. Set VS2_VOSEL = 1.4V + */ + mt6359p_write_field(PMIC_VS2_VOTER_CFG, 0x2C, 0x7F, 0); + mt6359p_write_field(PMIC_VS2_VOTER, 0, 0xFFF, 0); + mt6359p_write_field(PMIC_VS2_ELR0, 0x30, 0x7F, 0); +} + +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv) +{ + u32 vol_offset, vol_reg, vol; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + switch (buck_id) { + case MT6359P_GPU11: + vol_offset = 400000; + vol_reg = PMIC_VGPU11_ELR0; + break; + case MT6359P_SRAM_PROC1: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_ELR; + break; + case MT6359P_SRAM_PROC2: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_ELR; + break; + default: + die("ERROR: Unknown buck_id %u", buck_id); + return; + }; + + vol = (buck_uv - vol_offset) / 6250; + mt6359p_write_field(vol_reg, vol, 0x7F, 0); +} + +u32 mt6359p_buck_get_voltage(u32 buck_id) +{ + u32 vol_shift, vol_offset, vol_reg, vol; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + switch (buck_id) { + case MT6359P_GPU11: + vol_shift = 0; + vol_offset = 400000; + vol_reg = PMIC_VGPU11_DBG0; + break; + case MT6359P_SRAM_PROC1: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_VOSEL1; + break; + case MT6359P_SRAM_PROC2: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_VOSEL1; + break; + default: + die("ERROR: Unknown buck_id %u", buck_id); + return 0; + }; + + vol = mt6359p_read_field(vol_reg, 0x7F, vol_shift); + return vol_offset + vol * 6250; +} + +void mt6359p_set_vm18_voltage(u32 vm18_uv) +{ + u32 reg_vol, reg_cali; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + assert(vm18_uv >= 1700000); + assert(vm18_uv < 2000000); + + reg_vol = (vm18_uv / 1000 - VM18_VOL_OFFSET) / 100; + reg_cali = ((vm18_uv / 1000) % 100) / 10; + mt6359p_write(PMIC_VM18_ANA_CON0, (reg_vol << VM18_VOL_REG_SHIFT) | reg_cali); +} + +u32 mt6359p_get_vm18_voltage(void) +{ + u32 reg_vol, reg_cali; + + if (!pmif_arb) + die("ERROR: pmif_arb not initialized"); + + reg_vol = 100 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, VM18_VOL_REG_SHIFT); + reg_cali = 10 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, 0); + return 600 + reg_vol + reg_cali; +} + +static void init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + if (!pmif_arb) + die("ERROR: No spi device"); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi"); +} + +void mt6359p_init(void) +{ + init_pmif_arb(); + pmic_set_power_hold(); + pmic_wdt_set(); + pmic_init_setting(); + pmic_lp_setting(); + pmic_wk_vs2_voter_setting(); +} + +void mt6359p_romstage_init(void) +{ + init_pmif_arb(); +} diff --git a/src/soc/mediatek/mt8192/pmif.c b/src/soc/mediatek/mt8192/pmif.c new file mode 100644 index 0000000000..f6b1525915 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int pmif_check_swinf(struct pmif *arb, long timeout_us, u32 expected_status) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32(&arb->ch->ch_sta); + if (stopwatch_expired(&sw)) + return E_TIMEOUT; + } while (GET_SWINF_0_FSM(reg_rdata) != expected_status); + + return 0; +} + +static void pmif_send_cmd(struct pmif *arb, int write, u32 opc, u32 slvid, + u32 addr, u32 *rdata, u32 wdata, u32 len) +{ + int ret; + u32 data, bc = len - 1; + + /* Wait for Software Interface FSM state to be IDLE. */ + ret = pmif_check_swinf(arb, PMIF_WAIT_IDLE_US, SWINF_FSM_IDLE); + if (ret) { + printk(BIOS_ERR, "[%s] idle timeout\n", __func__); + return; + } + + /* Set the write data */ + if (write) + write32(&arb->ch->wdata, wdata); + + /* Send the command. */ + write32(&arb->ch->ch_send, + (opc << 30) | (write << 29) | (slvid << 24) | (bc << 16) | addr); + + if (!write) { + /* + * Wait for Software Interface FSM state to be WFVLDCLR, + * read the data and clear the valid flag. + */ + ret = pmif_check_swinf(arb, PMIF_READ_US, SWINF_FSM_WFVLDCLR); + if (ret) { + printk(BIOS_ERR, "[%s] read timeout\n", __func__); + return; + } + + data = read32(&arb->ch->rdata); + *rdata = data; + write32(&arb->ch->ch_rdy, 0x1); + } +} + +static void pmif_spmi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data) +{ + *data = 0; + pmif_send_cmd(arb, 0, PMIF_CMD_EXT_REG_LONG, slvid, reg, data, 0, 1); +} + +static void pmif_spmi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data) +{ + pmif_send_cmd(arb, 1, PMIF_CMD_EXT_REG_LONG, slvid, reg, NULL, data, 1); +} + +static u32 pmif_spmi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift) +{ + u32 data; + + pmif_spmi_read(arb, slvid, reg, &data); + data &= (mask << shift); + data >>= shift; + + return data; +} + +static void pmif_spmi_write_field(struct pmif *arb, u32 slvid, u32 reg, + u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + pmif_spmi_read(arb, slvid, reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + pmif_spmi_write(arb, slvid, reg, new); +} + +static void pmif_spi_read(struct pmif *arb, u32 slvid, u32 reg, u32 *data) +{ + *data = 0; + pmif_send_cmd(arb, 0, PMIF_CMD_REG_0, slvid, reg, data, 0, 1); +} + +static void pmif_spi_write(struct pmif *arb, u32 slvid, u32 reg, u32 data) +{ + pmif_send_cmd(arb, 1, PMIF_CMD_REG_0, slvid, reg, NULL, data, 1); +} + +static u32 pmif_spi_read_field(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift) +{ + u32 data; + + pmif_spi_read(arb, slvid, reg, &data); + data &= (mask << shift); + data >>= shift; + + return data; +} + +static void pmif_spi_write_field(struct pmif *arb, u32 slvid, u32 reg, + u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + pmif_spi_read(arb, slvid, reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + pmif_spi_write(arb, slvid, reg, new); +} + +static int is_pmif_init_done(struct pmif *arb) +{ + if (read32(&arb->mtk_pmif->init_done) & 0x1) + return 0; + + return -E_NODEV; +} + +static const struct pmif pmif_spmi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_BASE, + .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN, + .mstid = SPMI_MASTER_0, + .pmifid = PMIF_SPMI, + .write = pmif_spmi_write, + .read = pmif_spmi_read, + .write_field = pmif_spmi_write_field, + .read_field = pmif_spmi_read_field, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +static const struct pmif pmif_spi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, + .ch = (struct chan_regs *)PMIF_SPI_AP_CHAN, + .pmifid = PMIF_SPI, + .write = pmif_spi_write, + .read = pmif_spi_read, + .write_field = pmif_spi_write_field, + .read_field = pmif_spi_read_field, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +struct pmif *get_pmif_controller(int inf, int mstid) +{ + if (inf == PMIF_SPMI && mstid < ARRAY_SIZE(pmif_spmi_arb)) + return (struct pmif *)&pmif_spmi_arb[mstid]; + else if (inf == PMIF_SPI) + return (struct pmif *)&pmif_spi_arb[0]; + + die("[%s] Failed to get pmif controller: inf = %d, mstid = %d\n", __func__, inf, mstid); + return NULL; +} + +int mtk_pmif_init(void) +{ + int ret; + + ret = pmif_clk_init(); + if (!ret) + ret = pmif_spmi_init(get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0)); + if (!ret) + ret = pmif_spi_init(get_pmif_controller(PMIF_SPI, 0)); + + return ret; +} diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c new file mode 100644 index 0000000000..4e68f3e7b0 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_clk.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* APMIXED, ULPOSC1_CON0 */ +DEFINE_BITFIELD(OSC1_CALI, 6, 0) +DEFINE_BITFIELD(OSC1_IBAND, 13, 7) +DEFINE_BITFIELD(OSC1_FBAND, 17, 14) +DEFINE_BITFIELD(OSC1_DIV, 23, 18) +DEFINE_BIT(OSC1_CP_EN, 24) + +/* APMIXED, ULPOSC1_CON1 */ +DEFINE_BITFIELD(OSC1_32KCALI, 7, 0) +DEFINE_BITFIELD(OSC1_RSV1, 15, 8) +DEFINE_BITFIELD(OSC1_RSV2, 23, 16) +DEFINE_BITFIELD(OSC1_MOD, 25, 24) +DEFINE_BIT(OSC1_DIV2_EN, 26) + +/* APMIXED, ULPOSC1_CON2 */ +DEFINE_BITFIELD(OSC1_BIAS, 7, 0) + +/* SPM, POWERON_CONFIG_EN */ +DEFINE_BIT(BCLK_CG_EN, 0) +DEFINE_BITFIELD(PROJECT_CODE, 31, 16) + +/* SPM, ULPOSC_CON */ +DEFINE_BIT(ULPOSC_EN, 0) +DEFINE_BIT(ULPOSC_CG_EN, 2) + +/* INFRA, MODULE_SW_CG */ +DEFINE_BIT(PMIC_CG_TMR, 0) +DEFINE_BIT(PMIC_CG_AP, 1) +DEFINE_BIT(PMIC_CG_MD, 2) +DEFINE_BIT(PMIC_CG_CONN, 3) + +/* INFRA, INFRA_GLOBALCON_RST2 */ +DEFINE_BIT(PMIC_WRAP_SWRST, 0) +DEFINE_BIT(PMICSPMI_SWRST, 14) + +/* INFRA, PMICW_CLOCK_CTRL */ +DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0) + +/* TOPCKGEN, CLK_CFG_8 */ +DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 10, 8) +DEFINE_BIT(CLK_PWRAP_ULPOSC_INV, 12) +DEFINE_BIT(PDN_PWRAP_ULPOSC, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE1 */ +DEFINE_BIT(CLK_CFG_UPDATE1, 2) + +static void pmif_ulposc_config(void) +{ + /* ULPOSC1_CON0 */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CP_EN, 0, OSC1_DIV, 0xe, + OSC1_FBAND, 0x2, OSC1_IBAND, 0x52, OSC1_CALI, 0x40); + + /* ULPOSC1_CON1 */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_DIV2_EN, 0, OSC1_MOD, 0, + OSC1_RSV2, 0, OSC1_RSV1, 0x29, OSC1_32KCALI, 0); + + /* ULPOSC1_CON2 */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x40); +} + +static u32 pmif_get_ulposc_freq_mhz(u32 cali_val) +{ + u32 result = 0; + + /* set calibration value */ + SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val); + udelay(50); + result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK); + + return result / 1000; +} + +static int pmif_ulposc_cali(void) +{ + u32 current_val = 0, min = 0, max = CAL_MAX_VAL, middle; + int ret = 0, diff_by_min, diff_by_max, cal_result; + + do { + middle = (min + max) / 2; + if (middle == min) + break; + + current_val = pmif_get_ulposc_freq_mhz(middle); + if (current_val > FREQ_260MHZ) + max = middle; + else + min = middle; + } while (min <= max); + + diff_by_min = pmif_get_ulposc_freq_mhz(min) - FREQ_260MHZ; + diff_by_min = ABS(diff_by_min); + + diff_by_max = pmif_get_ulposc_freq_mhz(max) - FREQ_260MHZ; + diff_by_max = ABS(diff_by_max); + + if (diff_by_min < diff_by_max) { + cal_result = min; + current_val = pmif_get_ulposc_freq_mhz(min); + } else { + cal_result = max; + current_val = pmif_get_ulposc_freq_mhz(max); + } + + /* check if calibrated value is in the range of target value +- 15% */ + if (current_val < (FREQ_260MHZ * (1000 - CAL_TOL_RATE) / 1000) || + current_val > (FREQ_260MHZ * (1000 + CAL_TOL_RATE) / 1000)) { + printk(BIOS_ERR, "[%s] calibration fail: %dM\n", __func__, current_val); + ret = 1; + } + + return ret; +} + +static int pmif_init_ulposc(void) +{ + /* calibrate ULPOSC1 */ + pmif_ulposc_config(); + + /* enable spm swinf */ + if (!READ32_BITFIELD(&mtk_spm->poweron_config_en, BCLK_CG_EN)) + SET32_BITFIELDS(&mtk_spm->poweron_config_en, BCLK_CG_EN, 1, + PROJECT_CODE, 0xb16); + + /* turn on ulposc */ + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1); + udelay(100); + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1); + + return pmif_ulposc_cali(); +} + +int pmif_clk_init(void) +{ + if (pmif_init_ulposc()) + return E_NODEV; + + /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1, + PMIC_CG_MD, 1, PMIC_CG_CONN, 1); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_8, PDN_PWRAP_ULPOSC, 0, CLK_PWRAP_ULPOSC_INV, + 0, CLK_PWRAP_ULPOSC_SET, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1); + + /* use ULPOSC1 clock */ + SET32_BITFIELDS(&mt8192_infracfg->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf); + + /* toggle SPI/SPMI sw reset */ + SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1, + PMIC_WRAP_SWRST, 1); + SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1, + PMIC_WRAP_SWRST, 1); + + /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1, + PMIC_CG_MD, 1, PMIC_CG_CONN, 1); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spi.c b/src/soc/mediatek/mt8192/pmif_spi.c new file mode 100644 index 0000000000..72620041bd --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spi.c @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PMIF, SPI_MODE_CTRL */ +DEFINE_BIT(SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 5) +DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9) +DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10) +DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11) + +/* PMIF, SLEEP_PROTECTION_CTRL */ +DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) + +/* PMIF, OTHER_INF_EN */ +DEFINE_BITFIELD(INTGPSADCINF_EN, 5, 4) + +/* PMIF, STAUPD_CTRL */ +DEFINE_BITFIELD(STAUPD_CTRL_PRD, 3, 0) +DEFINE_BIT(STAUPD_CTRL_PMIC0_SIG_STA, 4) +DEFINE_BIT(STAUPD_CTRL_PMIC0_EINT_STA, 6) + +/* SPIMST, Manual_Mode_Access */ +DEFINE_BITFIELD(MAN_ACC_SPI_OP, 12, 8) +DEFINE_BIT(MAN_ACC_SPI_RW, 13) + +/* IOCFG_LM, PWRAP_SPI0_DRIVING */ +DEFINE_BITFIELD(PWRAP_SPI0_DRIVING, 2, 0) + +static void pmif_spi_config(struct pmif *arb) +{ + /* Set srclk_en always valid regardless of ulposc_sel_for_scp */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 0); + + /* Set SPI mode controlled by srclk_en and srvol_en instead of pmif_rdy */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, + SPI_MODE_CTRL_SRCLK_EN, 1, + SPI_MODE_CTRL_SRVOL_EN, 1, + SPI_MODE_CTRL_PMIF_RDY, 0); + + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0, + SCP_SLEEP_REQ_SEL, 0); + + /* Enable SWINF for AP */ + write32(&arb->mtk_pmif->inf_en, PMIF_SPI_AP); + + /* Enable arbitration for SWINF for AP */ + write32(&arb->mtk_pmif->arb_en, PMIF_SPI_AP); + + /* Enable PMIF_SPI Command Issue */ + write32(&arb->mtk_pmif->cmdissue_en, 1); +} + +static int check_idle(void *addr, u32 expected) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, PMIF_WAIT_IDLE_US); + do { + reg_rdata = read32(addr); + if (stopwatch_expired(&sw)) + return E_TIMEOUT; + } while ((reg_rdata & expected) != 0); + + return 0; +} + +static int reset_spislv(void) +{ + u32 pmicspi_mst_dio_en_backup; + + write32(&mtk_pmicspi_mst->wrap_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 1); + write32(&mtk_pmicspi_mst->man_en, 1); + pmicspi_mst_dio_en_backup = read32(&mtk_pmicspi_mst->dio_en); + write32(&mtk_pmicspi_mst->dio_en, 0); + + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_CSL); + /* Reset counter */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_CSH); + /* + * In order to pull CSN signal to PMIC, + * PMIC will count it then reset spi slave + */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, MAN_ACC_SPI_RW, OP_WR, + MAN_ACC_SPI_OP, OP_OUTS); + + /* Wait for PMIC SPI Master to be idle */ + if (check_idle(&mtk_pmicspi_mst->other_busy_sta_0, SPIMST_STA)) { + printk(BIOS_ERR, "[%s] spi master busy, timeout\n", __func__); + return E_TIMEOUT; + } + + write32(&mtk_pmicspi_mst->man_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 0); + write32(&mtk_pmicspi_mst->wrap_en, 1); + write32(&mtk_pmicspi_mst->dio_en, pmicspi_mst_dio_en_backup); + + return 0; +} + +static void init_reg_clock(struct pmif *arb) +{ + /* Set SoC SPI IO driving strength to 4 mA */ + SET32_BITFIELDS(&mtk_iocfg_lm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); + + /* Configure SPI protocol */ + write32(&mtk_pmicspi_mst->ext_ck_write, 1); + write32(&mtk_pmicspi_mst->ext_ck_read, 0); + write32(&mtk_pmicspi_mst->cshext_write, 0); + write32(&mtk_pmicspi_mst->cshext_read, 0); + write32(&mtk_pmicspi_mst->cslext_write, 0); + write32(&mtk_pmicspi_mst->cslext_read, 0x100); + + /* Set Read Dummy Cycle Number (Slave Clock is 18MHz) */ + arb->write(arb, DEFAULT_SLVID, PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + write32(&mtk_pmicspi_mst->rddmy, DUMMY_READ_CYCLES); + + /* Enable DIO mode */ + arb->write(arb, DEFAULT_SLVID, PMIC_DEW_DIO_EN, 0x1); + + /* Wait for completion of sending the commands */ + if (check_idle(&arb->mtk_pmif->inf_busy_sta, PMIF_SPI_AP)) { + printk(BIOS_ERR, "[%s] pmif channel busy, timeout\n", __func__); + return; + } + + if (check_idle(&arb->mtk_pmif->other_busy_sta_0, PMIF_CMD_STA)) { + printk(BIOS_ERR, "[%s] pmif cmd busy, timeout\n", __func__); + return; + } + + if (check_idle(&mtk_pmicspi_mst->other_busy_sta_0, SPIMST_STA)) { + printk(BIOS_ERR, "[%s] spi master busy, timeout\n", __func__); + return; + } + + write32(&mtk_pmicspi_mst->dio_en, 1); +} + +static void init_spislv(struct pmif *arb) +{ + /* Turn on SPI IO filter function */ + arb->write(arb, DEFAULT_SLVID, PMIC_FILTER_CON0, SPI_FILTER); + /* Turn on SPI IO SMT function to improve noise immunity */ + arb->write(arb, DEFAULT_SLVID, PMIC_SMT_CON1, SPI_SMT); + /* Turn off SPI IO pull function for power saving */ + arb->write(arb, DEFAULT_SLVID, PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + /* Enable SPI access in SODI-3.0 and Suspend modes */ + arb->write(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON0, 0x2); + /* Set SPI IO driving strength to 4 mA */ + arb->write(arb, DEFAULT_SLVID, PMIC_DRV_CON1, SPI_DRIVING); +} + +static int init_sistrobe(struct pmif *arb) +{ + u32 rdata = 0; + int si_sample_ctrl; + /* Random data for testing */ + const u32 test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27 + }; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pmicspi_mst->si_sampling_ctrl, si_sample_ctrl << 5); + + arb->read(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + /* + * Add the delay time of SPI data from PMIC to align the start boundary + * to current sampling clock edge. + */ + for (int si_dly = 0; si_dly < 10; si_dly++) { + arb->write(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON2, si_dly); + + int start_boundary_found = 0; + for (int i = 0; i < ARRAY_SIZE(test_data); i++) { + arb->write(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, test_data[i]); + arb->read(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + start_boundary_found = 1; + break; + } + } + if (start_boundary_found == 1) + break; + } + + /* + * Change the sampling clock edge to the next one which is the middle + * of SPI data window. + */ + write32(&mtk_pmicspi_mst->si_sampling_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + arb->read(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + printk(BIOS_ERR, "[%s] Failed for read test, data = %#x.\n", + __func__, rdata); + return E_READ_TEST_FAIL; + } + + return 0; +} + +static void init_staupd(struct pmif *arb) +{ + /* Unlock SPI Slave registers */ + arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0xbade); + + /* Enable CRC of PMIC 0 */ + arb->write(arb, DEFAULT_SLVID, PMIC_DEW_CRC_EN, 0x1); + + /* Wait for completion of sending the commands */ + if (check_idle(&arb->mtk_pmif->inf_busy_sta, PMIF_SPI_AP)) { + printk(BIOS_ERR, "[%s] pmif channel busy, timeout\n", __func__); + return; + } + + if (check_idle(&arb->mtk_pmif->other_busy_sta_0, PMIF_CMD_STA)) { + printk(BIOS_ERR, "[%s] pmif cmd busy, timeout\n", __func__); + return; + } + + if (check_idle(&mtk_pmicspi_mst->other_busy_sta_0, SPIMST_STA)) { + printk(BIOS_ERR, "[%s] spi master busy, timeout\n", __func__); + return; + } + + /* Configure CRC of PMIC Interface */ + write32(&arb->mtk_pmif->crc_ctrl, 0x1); + write32(&arb->mtk_pmif->sig_mode, 0x0); + + /* Lock SPI Slave registers */ + arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* Set up PMIC Siganature */ + write32(&arb->mtk_pmif->pmic_sig_addr, PMIC_DEW_CRC_VAL); + + /* Set up PMIC EINT */ + write32(&arb->mtk_pmif->pmic_eint_sta_addr, PMIC_INT_STA); + + SET32_BITFIELDS(&arb->mtk_pmif->staupd_ctrl, + STAUPD_CTRL_PRD, 5, + STAUPD_CTRL_PMIC0_SIG_STA, 1, + STAUPD_CTRL_PMIC0_EINT_STA, 1); +} + +int pmif_spi_init(struct pmif *arb) +{ + pmif_spi_config(arb); + + /* Reset spislv */ + if (reset_spislv()) + return E_SPI_INIT_RESET_SPI; + + /* Enable WRAP */ + write32(&mtk_pmicspi_mst->wrap_en, 0x1); + + /* SPI Waveform Configuration */ + init_reg_clock(arb); + + /* SPI Slave Configuration */ + init_spislv(arb); + + /* Input data calibration flow; */ + if (init_sistrobe(arb)) { + printk(BIOS_ERR, "[%s] data calibration fail\n", __func__); + return E_SPI_INIT_SIDLY; + } + + /* Lock SPISLV Registers */ + arb->write(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* + * Status update function initialization + * 1. Check signature using CRC (CRC 0 only) + * 2. Update EINT + * 3. Read back AUXADC thermal data for GPS + */ + init_staupd(arb); + + /* Configure PMIF Timer */ + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + + /* Enable interfaces and arbitration */ + write32(&arb->mtk_pmif->inf_en, PMIF_SPI_HW_INF | PMIF_SPI_MD | + PMIF_SPI_AP_SECURE | PMIF_SPI_AP); + + write32(&arb->mtk_pmif->arb_en, PMIF_SPI_HW_INF | PMIF_SPI_MD | PMIF_SPI_AP_SECURE | + PMIF_SPI_AP | PMIF_SPI_STAUPD | PMIF_SPI_TSX_HW | PMIF_SPI_DCXO_HW); + + /* Enable GPS AUXADC HW 0 and 1 */ + SET32_BITFIELDS(&arb->mtk_pmif->other_inf_en, INTGPSADCINF_EN, 0x3); + + /* Set INIT_DONE */ + write32(&arb->mtk_pmif->init_done, 0x1); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c new file mode 100644 index 0000000000..87b003bd3f --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) +#define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) + +/* IOCFG_BM, DRV_CFG2 */ +DEFINE_BITFIELD(SPMI_SCL, 5, 3) +DEFINE_BITFIELD(SPMI_SDA, 8, 6) + +/* TOPRGU, WDT_SWSYSRST2 */ +DEFINE_BIT(SPMI_MST_RST, 4) +DEFINE_BITFIELD(UNLOCK_KEY, 31, 24) + +/* TOPCKGEN, CLK_CFG_15 */ +DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_MST_INT, 12) +DEFINE_BIT(PDN_SPMI_MST, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE2 */ +DEFINE_BIT(SPMI_MST_CK_UPDATE, 30) + +/* SPMI_MST, SPMI_SAMPL_CTRL */ +DEFINE_BIT(SAMPL_CK_POL, 0) +DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1) + +/* PMIF, SPI_MODE_CTRL */ +DEFINE_BIT(SPI_MODE_CTRL, 7) +DEFINE_BIT(SRVOL_EN, 11) +DEFINE_BIT(SPI_MODE_EXT_CMD, 12) +DEFINE_BIT(SPI_EINT_MODE_GATING_EN, 13) + +/* PMIF, SLEEP_PROTECTION_CTRL */ +DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) + +static const struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_6, + .type = BUCK_CPU, + .type_id = BUCK_CPU_ID, + }, + { + .slvid = SPMI_SLAVE_7, + .type = BUCK_GPU, + .type_id = BUCK_GPU_ID, + }, +}; + +static int spmi_config_master(void) +{ + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x85); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15, + CLK_SPMI_MST_SEL, 0x7, + CLK_SPMI_MST_INT, 1, + PDN_SPMI_MST, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1); + + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x85); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + + return 0; +} + +static int spmi_read_check(struct pmif *pmif_arb, int slvid) +{ + u32 rdata = 0; + + pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST, &rdata); + if (rdata != MT6315_DEFAULT_VALUE_READ) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_NODEV; + } + + pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST_1, &rdata); + if (rdata != MT6315_DEFAULT_VALUE_READ) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_NODEV; + } + + return 0; +} + +static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb, const struct spmi_device *dev) +{ + int i; + bool success = false; + const struct cali cali_data[] = { + {SPMI_CK_DLY_1T, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_NEG}, + }; + + /* Indicate sampling clock polarity, 1: Positive 0: Negative */ + for (i = 0; i < ARRAY_SIZE(cali_data); i++) { + SET32_BITFIELDS(&mtk_spmi_mst->mst_sampl, SAMPL_CK_DLY, cali_data[i].dly, + SAMPL_CK_POL, cali_data[i].pol); + if (spmi_read_check(pmif_arb, dev->slvid) == 0) { + success = true; + break; + } + } + + if (!success) + die("ERROR - calibration fail for spmi clk"); + + return 0; +} + +static int spmi_mst_init(struct pmif *pmif_arb) +{ + int i; + + if (!pmif_arb) { + printk(BIOS_ERR, "%s: null pointer for pmif dev.\n", __func__); + return -E_INVAL; + } + + /* config IOCFG */ + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2); + spmi_config_master(); + + for (i = 0; i < ARRAY_SIZE(spmi_dev); i++) + spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]); + + return 0; +} + +static void pmif_spmi_force_normal_mode(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* listen srclken_0 only for entering normal or sleep mode */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, + SPI_MODE_CTRL, 0, + SRVOL_EN, 0, + SPI_MODE_EXT_CMD, 1, + SPI_EINT_MODE_GATING_EN, 1); + + /* enable spm/scp sleep request */ + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0, + SCP_SLEEP_REQ_SEL, 0); +} + +static void pmif_spmi_enable_swinf(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN); + write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN); +} + +static void pmif_spmi_enable_cmdIssue(int mstid, bool en) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* Enable cmdIssue */ + write32(&arb->mtk_pmif->cmdissue_en, en); +} + +static void pmif_spmi_enable(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + u32 cmd_per; + + /* clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); + + /* + * set bytecnt max limitation. + * hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ + write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0); + + /* Add latency limitation */ + write32(&arb->mtk_pmif->lat_cnter_en, PMIF_SPMI_INF); + write32(&arb->mtk_pmif->lat_limit_0, 0); + write32(&arb->mtk_pmif->lat_limit_1, 0x4); + write32(&arb->mtk_pmif->lat_limit_2, 0x8); + write32(&arb->mtk_pmif->lat_limit_4, 0x8); + write32(&arb->mtk_pmif->lat_limit_6, 0x3FF); + write32(&arb->mtk_pmif->lat_limit_9, 0x4); + write32(&arb->mtk_pmif->lat_limit_loading, PMIF_SPMI_INF); + + write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_INF); + write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_INF); + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + write32(&arb->mtk_pmif->init_done, 1); +} + +int pmif_spmi_init(struct pmif *arb) +{ + if (arb->is_pmif_init_done(arb) != 0) { + pmif_spmi_force_normal_mode(arb->mstid); + pmif_spmi_enable_swinf(arb->mstid); + pmif_spmi_enable_cmdIssue(arb->mstid, true); + pmif_spmi_enable(arb->mstid); + if (arb->is_pmif_init_done(arb)) + return -E_NODEV; + } + + if (spmi_mst_init(arb)) { + printk(BIOS_ERR, "[%s] failed to init spmi master\n", __func__); + return -E_NODEV; + } + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 919735d7d6..8763a9d71f 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index cac590cc6c..6750c3ef7a 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include struct qup qup[12] = { diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 342ee1f7fa..8cd9670f87 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index b80c3dfcbb..c9adba4fbf 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index d086a277c4..23914bbf2a 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 29d1452096..c00766a19d 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -27,66 +27,66 @@ struct rk3399_ddr_pi_regs { union noc_ddrtiminga0 { u32 d32; struct { - unsigned acttoact : 6; - unsigned reserved0 : 2; - unsigned rdtomiss : 6; - unsigned reserved1 : 2; - unsigned wrtomiss : 6; - unsigned reserved2 : 2; - unsigned readlatency : 8; + unsigned int acttoact : 6; + unsigned int reserved0 : 2; + unsigned int rdtomiss : 6; + unsigned int reserved1 : 2; + unsigned int wrtomiss : 6; + unsigned int reserved2 : 2; + unsigned int readlatency : 8; } b; }; union noc_ddrtimingb0 { u32 d32; struct { - unsigned rdtowr : 5; - unsigned reserved0 : 3; - unsigned wrtord : 5; - unsigned reserved1 : 3; - unsigned rrd : 4; - unsigned reserved2 : 4; - unsigned faw : 6; - unsigned reserved3 : 2; + unsigned int rdtowr : 5; + unsigned int reserved0 : 3; + unsigned int wrtord : 5; + unsigned int reserved1 : 3; + unsigned int rrd : 4; + unsigned int reserved2 : 4; + unsigned int faw : 6; + unsigned int reserved3 : 2; } b; }; union noc_ddrtimingc0 { u32 d32; struct { - unsigned burstpenalty : 4; - unsigned reserved0 : 4; - unsigned wrtomwr : 6; - unsigned reserved1 : 18; + unsigned int burstpenalty : 4; + unsigned int reserved0 : 4; + unsigned int wrtomwr : 6; + unsigned int reserved1 : 18; } b; }; union noc_devtodev0 { u32 d32; struct { - unsigned busrdtord : 3; - unsigned reserved0 : 1; - unsigned busrdtowr : 3; - unsigned reserved1 : 1; - unsigned buswrtord : 3; - unsigned reserved2 : 1; - unsigned buswrtowr : 3; - unsigned reserved3 : 17; + unsigned int busrdtord : 3; + unsigned int reserved0 : 1; + unsigned int busrdtowr : 3; + unsigned int reserved1 : 1; + unsigned int buswrtord : 3; + unsigned int reserved2 : 1; + unsigned int buswrtowr : 3; + unsigned int reserved3 : 17; } b; }; union noc_ddrmode { u32 d32; struct { - unsigned autoprecharge : 1; - unsigned bypassfiltering : 1; - unsigned fawbank : 1; - unsigned burstsize : 2; - unsigned mwrsize : 2; - unsigned reserved2 : 1; - unsigned forceorder : 8; - unsigned forceorderstate : 8; - unsigned reserved3 : 8; + unsigned int autoprecharge : 1; + unsigned int bypassfiltering : 1; + unsigned int fawbank : 1; + unsigned int burstsize : 2; + unsigned int mwrsize : 2; + unsigned int reserved2 : 1; + unsigned int forceorder : 8; + unsigned int forceorderstate : 8; + unsigned int reserved3 : 8; } b; }; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e61bc85829..b755fe1811 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -15,7 +15,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO config EHCI_BAR diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 8379d233f5..96737cfbb6 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -9,7 +9,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO if SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index cfe85a1952..6a1a9c848b 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -18,7 +18,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO config EHCI_BAR diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index df380c5bde..f5285c1355 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index a65f6725a5..c4a580a368 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -10,13 +10,13 @@ static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0xaa, port); } diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 523b7c46eb..dff75204a5 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -19,7 +19,7 @@ static void elog_add_boot_reason(void *unused) } /* Skip logging developer mode in ACPI resume path */ - if (dev && !acpi_is_wakeup()) { + if (dev && !acpi_is_wakeup_s3()) { elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); printk(BIOS_DEBUG, "%s: Logged dev mode boot\n", __func__); diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 2f73d39020..9bca42352d 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -71,7 +71,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) /* Try to read the SAR limit entry from VPD */ if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, buffer_size, VPD_RO_THEN_RW)) { - printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", + printk(BIOS_DEBUG, "Could not locate '%s' in VPD.\n", wifi_sar_limit_key); if (!CONFIG(WIFI_SAR_CBFS)) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index dc870f1ad1..53b73053c0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -36,6 +36,16 @@ are permitted provided that the following conditions are met: 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ } +/* Bit definitions for RasModes */ +#define CH_INDEPENDENT 0 +#define FULL_MIRROR_1LM BIT0 +#define FULL_MIRROR_2LM BIT1 +#define CH_LOCKSTEP BIT2 +#define RK_SPARE BIT3 +#define PARTIAL_MIRROR_1LM BIT5 +#define PARTIAL_MIRROR_2LM BIT6 +#define STAT_VIRT_LOCKSTEP BIT7 + #define MEMTYPE_1LM_MASK (1 << 0) #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) @@ -143,21 +153,23 @@ typedef struct SystemMemoryMapHob { UINT8 reserved2[22]; UINT8 DdrVoltage; - UINT8 reserved3[38]; + UINT8 reserved3[33]; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 reserved4[4]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved4[2213]; + UINT8 reserved5[2216]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved5[1603]; + UINT8 reserved6[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved6[24]; + UINT8 reserved7[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved7[5]; + UINT8 reserved8[5]; } SYSTEM_MEMORY_MAP_HOB; diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h deleted file mode 100644 index 1aa46a00a1..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F445055564E44 /* 'DNVUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F445055564E44 /* 'DNVUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F445055564E44 /* 'DNVUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h deleted file mode 100644 index 3aa74a0f3a..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h +++ /dev/null @@ -1,710 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - -#define MAX_CH 2 /* Maximum Number of Memory Channels */ -#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */ -#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */ - -/* - * Memory Down structures. - */ -typedef enum { - STATE_MEMORY_SLOT = 0, /* No memory down and a physical memory slot. */ - STATE_MEMORY_DOWN = 1, /* Memory down and not a physical memory slot. */ -} MemorySlotState; - -typedef struct { - MemorySlotState SlotState[MAX_CH][MAX_DIMM]; /* Memory Down state of - each DIMM in each - Channel */ - UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */ - UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Pointer to SPD Data for each - DIMM in each Channel */ -} MEMORY_DOWN_CONFIG; - -/* -* SMBIOS Memory Info structures. -*/ -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - UINT8 - ModulePartNum[20]; /* Module part number for DDR3 is 18 bytes - however for DRR4 20 bytes as per JEDEC Spec, - so reserving 20 bytes */ -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CH]; -} FSP_SMBIOS_MEMORY_INFO; - -/* -* GBE PCD supported states. -*/ -typedef enum { - BL_GBE0_GBE1_DISABLED, - BL_GBE0_GBE1_ENABLED, - BL_GBE1_DISABLED, -} BL_GBE_PCD_STATE; - -/* -* FIA MUX configuration structures. -*/ - -#define BL_ME_FIA_MUX_LANE_NUM_MAX 20 -#define BL_ME_FIA_MUX_LANE_NUM_MIN 1 -#define BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH 2 -#define BL_ME_FIA_MUX_LANE_MUX_SEL_MASK 0x3 -#define BL_ME_FIA_MUX_LANE_XHCI_ONLY 0xFF00000000 - -typedef enum { - BL_FIA_LANE00 = 0, - BL_FIA_LANE01, - BL_FIA_LANE02, - BL_FIA_LANE03, - BL_FIA_LANE04, - BL_FIA_LANE05, - BL_FIA_LANE06, - BL_FIA_LANE07, - BL_FIA_LANE08, - BL_FIA_LANE09, - BL_FIA_LANE10, - BL_FIA_LANE11, - BL_FIA_LANE12, - BL_FIA_LANE13, - BL_FIA_LANE14, - BL_FIA_LANE15, - BL_FIA_LANE16, - BL_FIA_LANE17, - BL_FIA_LANE18, - BL_FIA_LANE19, -} BL_ME_FIA_MUX_LANE_ORDER; - -#define BL_ME_FIA_MUX_LANE_SATA0_BEGING BL_FIA_LANE04 -#define BL_ME_FIA_MUX_LANE_SATA1_BEGING BL_FIA_LANE12 - -#define BL_FIA_LANE_CONFIG(Config, Lane) \ - ((UINT64)((UINT64)(Config) \ - << ((UINT64)(Lane) * (BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH)))) - -typedef union _BL_ME_FIA_MUX_CONFIG { - UINT64 MeFiaMuxLaneConfig; - struct { - UINT64 Lane00MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane01MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane02MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane03MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane04MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane05MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane06MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane07MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane08MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane09MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane10MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane11MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane12MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane13MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane14MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane15MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane16MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane17MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane18MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane19MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Reserved : 24; - } BL_MeFiaMuxLaneMuxSel; -} BL_ME_FIA_MUX_CONFIG; - -typedef enum { - BL_ME_FIA_MUX_LANE_DISCONNECTED, - BL_ME_FIA_MUX_LANE_PCIE, - BL_ME_FIA_MUX_LANE_SATA, - BL_ME_FIA_MUX_LANE_XHCI, -} BL_ME_FIA_MUX_LANE_CONFIG; - -#define BL_ME_FIA_SATA_LANE_SEL_WIDTH 2 -#define BL_ME_FIA_SATA_LANE_XHCI_ONLY 0x55000000 - -typedef enum { - BL_FIA_SATA_LANE04 = 0, - BL_FIA_SATA_LANE05, - BL_FIA_SATA_LANE06, - BL_FIA_SATA_LANE07, - BL_FIA_SATA_LANE08, - BL_FIA_SATA_LANE09, - BL_FIA_SATA_LANE10, - BL_FIA_SATA_LANE11, - BL_FIA_SATA_LANE12, - BL_FIA_SATA_LANE13, - BL_FIA_SATA_LANE14, - BL_FIA_SATA_LANE15, - BL_FIA_SATA_LANE16, - BL_FIA_SATA_LANE17, - BL_FIA_SATA_LANE18, - BL_FIA_SATA_LANE19 -} BL_ME_FIA_SATA_LANE_ORDER; - -#define BL_FIA_SATA_LANE_CONFIG(Config, Lane) \ - ((UINT32)((UINT32)(Config) \ - << ((UINT32)(Lane) * (BL_ME_FIA_SATA_LANE_SEL_WIDTH)))) - -typedef union _BL_ME_FIA_SATA_CONFIG { - UINT64 MeFiaSataLaneConfig; - struct { - UINT64 Lane04SataSel : 2; - UINT64 Lane05SataSel : 2; - UINT64 Lane06SataSel : 2; - UINT64 Lane07SataSel : 2; - UINT64 Lane08SataSel : 2; - UINT64 Lane09SataSel : 2; - UINT64 Lane10SataSel : 2; - UINT64 Lane11SataSel : 2; - UINT64 Lane12SataSel : 2; - UINT64 Lane13SataSel : 2; - UINT64 Lane14SataSel : 2; - UINT64 Lane15SataSel : 2; - UINT64 Lane16SataSel : 2; - UINT64 Lane17SataSel : 2; - UINT64 Lane18SataSel : 2; - UINT64 Lane19SataSel : 2; - UINT64 Reserved : 32; - } BL_MeFiaSataLaneSataSel; -} BL_ME_FIA_SATA_CONFIG; - -typedef enum { - BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED = 0, - BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED = 1, - BL_ME_FIA_SATA_CONTROLLER_LANE_SS_AND_GPIO_ASSIGNED = 3 -} BL_ME_FIA_SATA_LANE_CONFIG; - -#define BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH 4 -#define BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH 8 -#define BL_ME_FIA_PCIE_ROOT_CONFIG_XHCI_ONLY 0x0 - -typedef enum { - BL_FIA_PCIE_ROOT_PORT_0 = 0, - BL_FIA_PCIE_ROOT_PORT_1, - BL_FIA_PCIE_ROOT_PORT_2, - BL_FIA_PCIE_ROOT_PORT_3, - BL_FIA_PCIE_ROOT_PORT_4, - BL_FIA_PCIE_ROOT_PORT_5, - BL_FIA_PCIE_ROOT_PORT_6, - BL_FIA_PCIE_ROOT_PORT_7 -} BL_ME_FIA_PCIE_ROOT_PORT_ORDER; - -#define BL_FIA_PCIE_ROOT_PORT_CONFIG(Type, Config, PcieRootPort) \ - (((Type) == BL_ME_FIA_PCIE_ROOT_PORT_STATE) \ - ? ((UINT64)((UINT64)(Config) << (UINT64)(PcieRootPort))) \ - : ((UINT64)( \ - (UINT64)(Config) << (UINT64)( \ - ((UINT64)(PcieRootPort) * \ - (BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH)) + \ - BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH)))) - -typedef union _BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG { - UINT64 MeFiaPcieRootPortsConfig; - struct { - UINT64 PcieRp0En : 1; - UINT64 PcieRp1En : 1; - UINT64 PcieRp2En : 1; - UINT64 PcieRp3En : 1; - UINT64 PcieRp4En : 1; - UINT64 PcieRp5En : 1; - UINT64 PcieRp6En : 1; - UINT64 PcieRp7En : 1; - UINT64 PcieRp0LinkWidth : 4; - UINT64 PcieRp1LinkWidth : 4; - UINT64 PcieRp2LinkWidth : 4; - UINT64 PcieRp3LinkWidth : 4; - UINT64 PcieRp4LinkWidth : 4; - UINT64 PcieRp5LinkWidth : 4; - UINT64 PcieRp6LinkWidth : 4; - UINT64 PcieRp7LinkWidth : 4; - UINT64 Reserved : 24; - } BL_MeFiaPcieRpConfig; -} BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH -} BL_ME_FIA_PCIE_ROOT_PORT_CONFIG_TYPE; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED -} BL_ME_FIA_PCIE_ROOT_PORT_STATE_CONFIG; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL = 0, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1 = 0xF -} BL_ME_FIA_PCIE_ROOT_PORT_LINK_CONFIG; - -typedef struct _BL_ME_FIA_CONFIG { - BL_ME_FIA_MUX_CONFIG MuxConfiguration; - BL_ME_FIA_SATA_CONFIG SataLaneConfiguration; - BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG PcieRootPortsConfiguration; -} BL_ME_FIA_CONFIG; - -/* - * The FIA_MUX_CONFIG block describes the expected configuration of - * FIA MUX configuration. - */ -typedef struct { - UINT32 SkuNumLanesAllowed; // Platform view of Num Lanes allowed - BL_ME_FIA_CONFIG FiaMuxConfig; // Current Platform FIA MUX Configuration - BL_ME_FIA_CONFIG FiaMuxConfigRequest; // FIA MUX Configuration Requested -} BL_FIA_MUX_CONFIG; - -/* - * The FIA_MUX_CONFIG_STATUS describes the status of configuring - * FIA MUX configuration. -*/ -typedef struct { - UINT64 FiaMuxConfigGetStatus; // Status returned from FiaMuxConfigGet, - // if not EFI_SUCCESS, then error occurred - // and user can decide on next steps - UINT64 FiaMuxConfigSetStatus; // Status returned from FiaMuxConfigSet, - // if not EFI_SUCCESS, then error occurred - // and user can decide on next steps - BOOLEAN FiaMuxConfigSetRequired; // Boolean: true - a FiaMuxConfigSet - // was required, false otherwise -} BL_FIA_MUX_CONFIG_STATUS; - -/* -* FIA MUX Config HOB structure -*/ -typedef struct { - BL_FIA_MUX_CONFIG FiaMuxConfig; - BL_FIA_MUX_CONFIG_STATUS FiaMuxConfigStatus; -} BL_FIA_MUX_CONFIG_HOB; - -/* PCIe port bifurcation codes - matches setup option values */ -#define PCIE_BIF_CTRL_x2x2x2x2 0 -#define PCIE_BIF_CTRL_x2x2x4 1 -#define PCIE_BIF_CTRL_x4x2x2 2 -#define PCIE_BIF_CTRL_x4x4 3 -#define PCIE_BIF_CTRL_x8 4 - -#define BL_MAX_PCIE_CTRL 2 - -/* - * HSIO INFORMATION structure - */ -typedef enum { - BL_SKU_HSIO_06 = 6, - BL_SKU_HSIO_08 = 8, - BL_SKU_HSIO_10 = 10, - BL_SKU_HSIO_12 = 12, - BL_SKU_HSIO_20 = 20, -} BL_SKU_HSIO_LANE_NUMBER; - -typedef struct { - UINT16 NumLanesSupported; - UINT8 PcieBifCtr[BL_MAX_PCIE_CTRL]; - BL_ME_FIA_CONFIG FiaConfig; -} BL_HSIO_INFORMATION; - -/* - * eMMC DLL structure for EMMC DLL registers settings - */ -typedef struct { - UINT32 TxCmdCntl; - UINT32 TxDataCntl1; - UINT32 TxDataCntl2; - UINT32 RxCmdDataCntl1; - UINT32 RxStrobeCntl; - UINT32 RxCmdDataCntl2; - UINT32 MasterSwCntl; -} BL_EMMC_DLL_CONFIG; - -typedef struct { - UINT16 Signature; - BL_EMMC_DLL_CONFIG eMMCDLLConfig; -} BL_EMMC_INFORMATION; - -typedef enum { - BL_FAST_BOOT_CHECKER_NORMAL = 0, - BL_FAST_BOOT_CHECKER_WARNING, - BL_FAST_BOOT_CHECKER_CRITICAL -} BL_FAST_BOOT_CHECKER; - -#define BL_MAX_SCRUB_SEGMENTS 5 - -typedef struct { - UINT16 Start; // Determines the low range for a memory segment (in MB) - UINT16 End; // Determines the high range for a memory segment (in MB) -} BL_SCRUB_SEGMENT; - -typedef struct { - UINT8 NumberOfSegments; - UINT8 Reserved; - BL_SCRUB_SEGMENT ScrubSegment[BL_MAX_SCRUB_SEGMENTS]; -} BL_MEMORY_SCRUB_SEGMENTS; - -/** Fsp M Configuration -**/ -typedef struct { - - /** Offset 0x0040 - Tseg Size - Size of SMRAM memory reserved. - 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB - **/ - UINT8 PcdSmmTsegSize; - - /** Offset 0x0041 - FSP Debug Print Level - Select the FSP debug message print level. - 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG - **/ - UINT8 PcdFspDebugPrintErrorLevel; - - /** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_0_0; - - /** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_0_1; - - /** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_1_0; - - /** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_1_1; - - /** Offset 0x0046 - Enable Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS - **/ - UINT8 PcdMrcRmtSupport; - - /** Offset 0x0047 - RMT CPGC exp_loop_cnt - Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1). - 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, - 13:13, 14:14, 15:15 - **/ - UINT8 PcdMrcRmtCpgcExpLoopCntValue; - - /** Offset 0x0048 - RMT CPGC num_bursts - Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1). - 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, - 13:13, 14:14, 15:15 - **/ - UINT8 PcdMrcRmtCpgcNumBursts; - - /** Offset 0x0049 - Preserve Memory Across Reset - Enable/disable memory preservation across reset. - $EN_DIS - **/ - UINT8 PcdMemoryPreservation; - - /** Offset 0x004A - Fast Boot - Enable/disable Fast Boot function. Once enabled, all following boots - will use the - presaved MRC data to improve the boot performance. - $EN_DIS - **/ - UINT8 PcdFastBoot; - - /** Offset 0x004B - ECC Support - Enable/disable ECC Support. - $EN_DIS - **/ - UINT8 PcdEccSupport; - - /** Offset 0x004C - HSUART Device - Select the PCI High Speed UART Device for Serial Port. - 0:HSUART0, 1:HSUART1, 2:HSUART2 - **/ - UINT8 PcdHsuartDevice; - - /** Offset 0x004D - Memory Down - Enable/disable Memory Down function. - $EN_DIS - **/ - UINT8 PcdMemoryDown; - - /** Offset 0x004E - **/ - UINT32 PcdMemoryDownConfigPtr; - - /** Offset 0x0052 - SATA Controller 0 - Enable/disable SATA Controller 0. - $EN_DIS - **/ - UINT8 PcdEnableSATA0; - - /** Offset 0x0053 - SATA Controller 1 - Enable/disable SATA Controller 1. - $EN_DIS - **/ - UINT8 PcdEnableSATA1; - - /** Offset 0x0054 - Intel Quick Assist Technology - Enable/disable Intel Quick Assist Technology. - $EN_DIS - **/ - UINT8 PcdEnableIQAT; - - /** Offset 0x0055 - SPD Write Disable - Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = - [FORCE_DISABLE]) - 0:Force Enable, 1:Force Disable - **/ - UINT8 PcdSmbusSpdWriteDisable; - - /** Offset 0x0056 - ME_SHUTDOWN Message - Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP - Integration Guide - for details. - $EN_DIS - **/ - UINT8 PcdEnableMeShutdown; - - /** Offset 0x0057 - XHCI Controller - Enable / Disable XHCI controller - $EN_DIS - **/ - UINT8 PcdEnableXhci; - - /** Offset 0x0058 - Memory Frequency - Set DDR Memory Frequency, refer to FSP Integration Guide for details. - 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400 - **/ - UINT8 PcdDdrFreq; - - /** Offset 0x0059 - MMIO Size - Set memory mapped IO space size - 0:2048M, 1:1024M, 2:3072M - **/ - UINT8 PcdMmioSize; - - /** Offset 0x005A - ME HECI Communication - Enable/Disable ME HECI communication - $EN_DIS - **/ - UINT8 PcdMeHeciCommunication; - - /** Offset 0x005B - HSIO Lanes Number - HSIO lanes number of SKU - 6:6, 8:8, 10:10, 12:12, 20:20 - **/ - UINT8 PcdHsioLanesNumber; - - /** Offset 0x005C - **/ - UINT32 PcdFiaMuxConfigPtr; - - /** Offset 0x0060 - Customer Revision - The Customer can set this revision string for their own purpose. - **/ - UINT8 PcdCustomerRevision[32]; - - /** Offset 0x0080 - 32-Bit bus mode - Enable/Disable 32-Bit bus memory mode. - $EN_DIS - **/ - UINT8 PcdHalfWidthEnable; - - /** Offset 0x0081 - TCL Performance - Enable/Disable Tcl timing for performance. - $EN_DIS - **/ - UINT8 PcdTclIdle; - - /** Offset 0x0082 - Interleave Mode - Select Interleave Mode - 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2 - **/ - UINT8 PcdInterleaveMode; - - /** Offset 0x0083 - Memory Thermal Throttling - Enable/disable Memory Thermal Throttling management mode - $EN_DIS - **/ - UINT8 PcdMemoryThermalThrottling; - - /** Offset 0x0084 - Memory Test - Enable / Disable Memory Test, refer to FSP Integration Guide for - details. - $EN_DIS - **/ - UINT8 PcdSkipMemoryTest; - - /** Offset 0x0085 - **/ - BL_MEMORY_SCRUB_SEGMENTS *PcdScrubSegmentPtr; - - /** Offset 0x0089 - USB2 Port 1 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port1Pin; - - /** Offset 0x008A - USB2 Port 2 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port2Pin; - - /** Offset 0x008B - USB2 Port 3 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port3Pin; - - /** Offset 0x008C - USB2 Port 4 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port4Pin; - - /** Offset 0x008D - USB3 Port 1 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port1Pin; - - /** Offset 0x008E - USB3 Port 2 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port2Pin; - - /** Offset 0x008F - USB3 Port 3 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port3Pin; - - /** Offset 0x0090 - USB3 Port 4 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port4Pin; - - /** Offset 0x0091 - IOxAPIC 0-199 - Enable/disable IOxAPIC 24-119 entries - $EN_DIS - **/ - UINT8 PcdIOxAPIC0_199; - - /** Offset 0x0092 - DMAP_X16 - Enable/Disable DMAP_X16 dynamic MRC field indicating memory device - width is x16 or not - $EN_DIS - **/ - UINT8 PcdDmapX16; - - /** Offset 0x0093 - **/ - UINT8 UnusedUpdSpace0[333]; - - /** Offset 0x01E0 - **/ - UINT8 ReservedMemoryInitUpd[16]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSPM_ARCH_UPD FspmArchUpd; - - /** Offset 0x0040 - **/ - FSP_M_CONFIG FspmConfig; - - /** Offset 0x01F0 - **/ - UINT8 UnusedUpdSpace1[14]; - - /** Offset 0x01FE - **/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h deleted file mode 100644 index f76f1a5e55..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h +++ /dev/null @@ -1,289 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - -/** Fsp S Configuration -**/ -typedef struct { - - /** Offset 0x0020 - PCIe Controller 0 Bifurcation - Configure PCI Express controller 0 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 - **/ - UINT8 PcdBifurcationPcie0; - - /** Offset 0x0021 - PCIe Controller 1 Bifurcation - Configure PCI Express controller 1 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 - **/ - UINT8 PcdBifurcationPcie1; - - /** Offset 0x0022 - Active Core Count - Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) - 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, - 12:12, 13:13, - 14:14, 15:15 - **/ - UINT8 PcdActiveCoreCount; - - /** Offset 0x0023 - **/ - UINT32 PcdCpuMicrocodePatchBase; - - /** Offset 0x0027 - **/ - UINT32 PcdCpuMicrocodePatchSize; - - /** Offset 0x002B - PCIe Controller 0 - Enable / Disable PCI Express controller 0 - $EN_DIS - **/ - UINT8 PcdEnablePcie0; - - /** Offset 0x002C - PCIe Controller 1 - Enable / Disable PCI Express controller 1 - $EN_DIS - **/ - UINT8 PcdEnablePcie1; - - /** Offset 0x002D - Embedded Multi-Media Controller (eMMC) - Enable / Disable Embedded Multi-Media controller - $EN_DIS - **/ - UINT8 PcdEnableEmmc; - - /** Offset 0x002E - LAN Controllers - Enable / Disable LAN controllers, refer to FSP Integration Guide for - details. - 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only - **/ - UINT8 PcdEnableGbE; - - /** Offset 0x002F - **/ - UINT32 PcdFiaMuxConfigRequestPtr; - - /** Offset 0x0033 - **/ - UINT8 UnusedUpdSpace0[4]; - - /** Offset 0x0037 - PCIe Root Port 0 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort0DeEmphasis; - - /** Offset 0x0038 - PCIe Root Port 1 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort1DeEmphasis; - - /** Offset 0x0039 - PCIe Root Port 2 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort2DeEmphasis; - - /** Offset 0x003A - PCIe Root Port 3 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort3DeEmphasis; - - /** Offset 0x003B - PCIe Root Port 4 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort4DeEmphasis; - - /** Offset 0x003C - PCIe Root Port 5 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort5DeEmphasis; - - /** Offset 0x003D - PCIe Root Port 6 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort6DeEmphasis; - - /** Offset 0x003E - PCIe Root Port 7 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort7DeEmphasis; - - /** Offset 0x003F - **/ - UINT8 UnusedUpdSpace1; - - /** Offset 0x0040 - **/ - UINT32 PcdEMMCDLLConfigPtr; - - /** Offset 0x0044 - PCIe Root Port 0 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort0LinkSpeed; - - /** Offset 0x0045 - PCIe Root Port 1 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort1LinkSpeed; - - /** Offset 0x0046 - PCIe Root Port 2 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort2LinkSpeed; - - /** Offset 0x0047 - PCIe Root Port 3 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort3LinkSpeed; - - /** Offset 0x0048 - PCIe Root Port 4 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort4LinkSpeed; - - /** Offset 0x0049 - PCIe Root Port 5 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort5LinkSpeed; - - /** Offset 0x004A - PCIe Root Port 6 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort6LinkSpeed; - - /** Offset 0x004B - PCIe Root Port 7 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort7LinkSpeed; - - /** Offset 0x004C - PCIe Root Port 0 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort0Aspm; - - /** Offset 0x004D - PCIe Root Port 1 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort1Aspm; - - /** Offset 0x004E - PCIe Root Port 2 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort2Aspm; - - /** Offset 0x004F - PCIe Root Port 3 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort3Aspm; - - /** Offset 0x0050 - PCIe Root Port 4 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort4Aspm; - - /** Offset 0x0051 - PCIe Root Port 5 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort5Aspm; - - /** Offset 0x0052 - PCIe Root Port 6 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort6Aspm; - - /** Offset 0x0053 - PCIe Root Port 7 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort7Aspm; - - /** Offset 0x0054 - **/ - UINT8 UnusedUpdSpace2[140]; - - /** Offset 0x00E0 - **/ - UINT8 ReservedSiliconInitUpd[16]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSP_S_CONFIG FspsConfig; - - /** Offset 0x00F0 - **/ - UINT8 UnusedUpdSpace3[14]; - - /** Offset 0x00FE - **/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h deleted file mode 100644 index f06f72bd3f..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - -/** Fsp T Core UPD -**/ -typedef struct { - - /** Offset 0x0020 - **/ - UINT32 MicrocodeRegionBase; - - /** Offset 0x0024 - **/ - UINT32 MicrocodeRegionLength; - - /** Offset 0x0028 - **/ - UINT32 CodeRegionBase; - - /** Offset 0x002C - **/ - UINT32 CodeRegionLength; - - /** Offset 0x0030 - **/ - UINT8 Reserved1[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - - /** Offset 0x0040 - Disable Port80 output in FSP-T - Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, - 2:Disable Port80 - Output, refer to FSP Integration Guide for details - 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output - **/ - UINT8 PcdFsptPort80RouteDisable; - - /** Offset 0x0041 - **/ - UINT8 ReservedTempRamInitUpd[31]; -} FSPT_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSPT_CORE_UPD FsptCoreUpd; - - /** Offset 0x0040 - **/ - FSPT_CONFIG FsptConfig; - - /** Offset 0x0060 - **/ - UINT8 UnusedUpdSpace0[30]; - - /** Offset 0x007E - **/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index fc167c5b14..55f841835e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -308,9 +308,26 @@ typedef struct { **/ UINT8 VtdDisable; -/** Offset 0x00E1 - Reserved +/** Offset 0x00E1 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS **/ - UINT8 Reserved3[3]; + UINT8 VtdIgdEnable; + +/** Offset 0x00E2 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x00E3 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; /** Offset 0x00E4 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -406,7 +423,7 @@ typedef struct { /** Offset 0x00F5 - Reserved **/ - UINT8 Reserved4[3]; + UINT8 Reserved3[3]; /** Offset 0x00F8 - MMA Test Content Pointer Pointer to MMA Test Content in Memory @@ -614,7 +631,7 @@ typedef struct { /** Offset 0x012B - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved4; /** Offset 0x012C - HECI1 BAR address BAR address of HECI1 @@ -671,7 +688,7 @@ typedef struct { /** Offset 0x0141 - Reserved **/ - UINT8 Reserved6[3]; + UINT8 Reserved5[3]; /** Offset 0x0144 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 @@ -694,7 +711,7 @@ typedef struct { /** Offset 0x014E - Reserved **/ - UINT8 Reserved7[24]; + UINT8 Reserved6[24]; /** Offset 0x0166 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): @@ -772,7 +789,7 @@ typedef struct { /** Offset 0x017C - Reserved **/ - UINT8 Reserved8[10]; + UINT8 Reserved7[10]; /** Offset 0x0186 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support @@ -782,7 +799,7 @@ typedef struct { /** Offset 0x0187 - Reserved **/ - UINT8 Reserved9; + UINT8 Reserved8; /** Offset 0x0188 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -792,7 +809,7 @@ typedef struct { /** Offset 0x0189 - Reserved **/ - UINT8 Reserved10[2]; + UINT8 Reserved9[2]; /** Offset 0x018B - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable @@ -832,7 +849,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved10; /** Offset 0x0192 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable @@ -872,7 +889,7 @@ typedef struct { /** Offset 0x0198 - Reserved **/ - UINT8 Reserved12[130]; + UINT8 Reserved11[130]; /** Offset 0x021A - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 @@ -1045,7 +1062,7 @@ typedef struct { /** Offset 0x024D - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved12; /** Offset 0x024E - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. @@ -1113,7 +1130,7 @@ typedef struct { /** Offset 0x025F - Reserved **/ - UINT8 Reserved14[9]; + UINT8 Reserved13[9]; /** Offset 0x0268 - CPU Run Control Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: @@ -1146,7 +1163,7 @@ typedef struct { /** Offset 0x026D - Reserved **/ - UINT8 Reserved15[3]; + UINT8 Reserved14[3]; /** Offset 0x0270 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1210,7 +1227,7 @@ typedef struct { /** Offset 0x02A9 - Reserved **/ - UINT8 Reserved16[6]; + UINT8 Reserved15[6]; /** Offset 0x02AF - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1392,7 +1409,7 @@ typedef struct { /** Offset 0x0492 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved16[2]; /** Offset 0x0494 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1418,7 +1435,7 @@ typedef struct { /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved18[5]; + UINT8 Reserved17[5]; /** Offset 0x04BC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1447,7 +1464,7 @@ typedef struct { /** Offset 0x04C3 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x04C4 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1475,7 +1492,7 @@ typedef struct { /** Offset 0x04CB - Reserved **/ - UINT8 Reserved20[5]; + UINT8 Reserved19[5]; /** Offset 0x04D0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -1686,7 +1703,7 @@ typedef struct { /** Offset 0x04F3 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved20; /** Offset 0x04F4 - Margin Limit L2 % of L1 check for margin limit check @@ -1920,7 +1937,7 @@ typedef struct { /** Offset 0x051B - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; /** Offset 0x051C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -1943,7 +1960,7 @@ typedef struct { /** Offset 0x051F - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved22; /** Offset 0x0520 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -1953,7 +1970,7 @@ typedef struct { /** Offset 0x0522 - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved23[2]; /** Offset 0x0524 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) @@ -1980,7 +1997,7 @@ typedef struct { /** Offset 0x052B - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved24; /** Offset 0x052C - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on @@ -2371,7 +2388,7 @@ typedef struct { /** Offset 0x0576 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x0577 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, @@ -2438,7 +2455,7 @@ typedef struct { /** Offset 0x0581 - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved26; /** Offset 0x0582 - Post Code Output Port This option configures Post Code Output Port @@ -2458,7 +2475,7 @@ typedef struct { /** Offset 0x0586 - Reserved **/ - UINT8 Reserved28[18]; + UINT8 Reserved27[18]; /** Offset 0x0598 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it @@ -2485,7 +2502,7 @@ typedef struct { /** Offset 0x059D - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved28[2]; /** Offset 0x059F - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -2498,7 +2515,7 @@ typedef struct { /** Offset 0x05A0 - Reserved **/ - UINT8 Reserved30[18]; + UINT8 Reserved29[18]; /** Offset 0x05B2 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2515,7 +2532,7 @@ typedef struct { /** Offset 0x05B4 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x05B5 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -2526,7 +2543,7 @@ typedef struct { /** Offset 0x05B6 - Reserved **/ - UINT8 Reserved32[100]; + UINT8 Reserved31[100]; /** Offset 0x061A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2549,7 +2566,7 @@ typedef struct { /** Offset 0x061F - Reserved **/ - UINT8 Reserved33[11]; + UINT8 Reserved32[11]; /** Offset 0x062A - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2591,7 +2608,7 @@ typedef struct { /** Offset 0x0630 - Reserved **/ - UINT8 Reserved34[3]; + UINT8 Reserved33[3]; /** Offset 0x0633 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -2600,7 +2617,7 @@ typedef struct { /** Offset 0x0635 - Reserved **/ - UINT8 Reserved35[19]; + UINT8 Reserved34[19]; /** Offset 0x0648 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. @@ -2610,7 +2627,7 @@ typedef struct { /** Offset 0x0649 - Reserved **/ - UINT8 Reserved36[11]; + UINT8 Reserved35[11]; /** Offset 0x0654 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 @@ -2692,7 +2709,7 @@ typedef struct { /** Offset 0x0669 - Reserved **/ - UINT8 Reserved37[19]; + UINT8 Reserved36[19]; /** Offset 0x067C - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -2708,7 +2725,7 @@ typedef struct { /** Offset 0x067E - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved37; /** Offset 0x067F - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings @@ -2718,7 +2735,7 @@ typedef struct { /** Offset 0x0680 - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved38[16]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 6038b13eff..35cc43bcbb 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ typedef struct { /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[36]; + UINT8 Reserved45[44]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0940 +/** Offset 0x0948 **/ UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0946 +/** Offset 0x094E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b7ef0008f9..276ac79c4c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1058,10 +1058,10 @@ typedef struct { UINT16 ITbtDmaLtr[2]; /** Offset 0x04E2 - Enable/Disable CrashLog - Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + Deprecated. Move to PreMem $EN_DIS **/ - UINT8 CpuCrashLogEnable; + UINT8 DeprecatedCpuCrashLogEnable; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -2838,7 +2838,7 @@ typedef struct { /** Offset 0x0B95 - Configuration for boot TDP selection Deprecated. Move to premem. **/ - UINT8 ConfigTdpLevel; + UINT8 DeprecatedConfigTdpLevel; /** Offset 0x0B96 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index b3470d54cc..c2ce32befb 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -187,13 +187,6 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, } else { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { - fw_type = AMD_BIOS_MP2_CFG; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { fw_type = AMD_DRIVER_ENTRIES; subprog = 0; @@ -267,6 +260,13 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, fw_type = AMD_BIOS_PMUD; subprog = 1; instance = 4; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else { fw_type = AMD_BIOS_INVALID; } diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c index b4e10a2c0e..76089ea340 100644 --- a/util/cbfstool/amdcompress.c +++ b/util/cbfstool/amdcompress.c @@ -29,9 +29,9 @@ static const char *optstring = "i:o:cm:uh"; static struct option long_options[] = { {"infile", required_argument, 0, 'i' }, {"outfile", required_argument, 0, 'o' }, - {"compress", required_argument, 0, 'c' }, - {"maxsize", required_argument, 0, 'h' }, - {"uncompress", required_argument, 0, 'u' }, + {"compress", no_argument, 0, 'c' }, + {"maxsize", required_argument, 0, 'm' }, + {"uncompress", no_argument, 0, 'u' }, {"help", no_argument, 0, 'h' }, }; diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 43d373ee84..fb530c54c1 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -90,12 +90,12 @@ func ioApicRoute() bool { macro.Add("_APIC") if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL { if dw0.GetRxInvert() != 0 { - // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) + // PAD_CFG_GPI_APIC_LOW(pad, pull, rst) macro.Add("_LOW") } else { + // PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) macro.Add("_HIGH") } - // PAD_CFG_GPI_APIC(pad, pull, rst) macro.Add("(").Id().Pull().Rstsrc().Add("),") return true } @@ -123,18 +123,8 @@ func sciRoute() bool { if dw0.GetGPIOInputRouteSCI() == 0 { return false } - macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - macro.Trig() - } - // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), - // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ - // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - macro.Add(",").Add("EDGE_SINGLE") - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } @@ -145,16 +135,8 @@ func smiRoute() bool { if dw0.GetGPIOInputRouteSMI() == 0 { return false } - macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), - macro.Add(",").Add("EDGE_SINGLE") - } - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - // e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), - macro.Trig() - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 1fd4404942..815bfc7e55 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1558,6 +1558,12 @@ static void update_device(struct device *base_dev, struct device *override_dev) */ base_dev->enabled = override_dev->enabled; + /* + * Copy the hidden state of override device to base device. This allows + * override tree to hide or unhide a particular device. + */ + base_dev->hidden = override_dev->hidden; + /* * Copy subsystem vendor and device ids from override device to base * device only if the ids are non-zero in override device. Else, honor diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 109fadb916..91062d0000 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -181,6 +181,42 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "H9HCNNNCRMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "H9HCNNNFBMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } + }, + { + "name": "MT53D1G64D4NW-046 WT:A", + "attribs": { + "densityPerChannelGb": 16, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] }