Add code to read Intel microcode from CBFS

When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in
CBFS and pass it to intel_update_microcode() instead of using the
compiled in array.

CBFS accesses in pre-RAM and 'normal' environments are provided
through different API.

Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1296
Tested-by: build bot (Jenkins)

src/cpu/intel/model_206ax/bootblock.c

@@ -23,9 +23,11 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 
+#if !CONFIG_MICROCODE_IN_CBFS
 static const uint32_t microcode_updates[] = {
 	#include "microcode_blob.h"
 };
+#endif
 
 #include <cpu/intel/microcode/microcode.c>
 
@@ -61,5 +63,9 @@ static void enable_rom_caching(void)
 static void bootblock_cpu_init(void)
 {
 	enable_rom_caching();
+#if CONFIG_MICROCODE_IN_CBFS
+	intel_update_microcode_from_cbfs();
+#else
 	intel_update_microcode(microcode_updates);
+#endif
 }

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -115,9 +115,11 @@ static acpi_cstate_t cstate_map[] = {
 	{ 0 }
 };
 
+#if !CONFIG_MICROCODE_IN_CBFS
 static const uint32_t microcode_updates[] = {
 	#include "microcode_blob.h"
 };
+#endif
 
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
@@ -387,8 +389,11 @@ static void model_206ax_init(device_t cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
+#if CONFIG_MICROCODE_IN_CBFS
+	intel_update_microcode_from_cbfs();
+#else
 	intel_update_microcode(microcode_updates);
+#endif
 
 	/* Clear out pending MCEs */
 	configure_mca();