soc/amd/genoa: Add PCI interrupt support
This patch adds PCI interrupt details as per the Processor Programming Reference (PPR) version 0.25 (#55901), table 319. Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Varshit Pandya
committed by
Felix Held
Felix Held
parent
d581878264
commit
5397b4dcf2
98
src/soc/amd/genoa/acpi/pci_int_defs.asl
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98
src/soc/amd/genoa/acpi/pci_int_defs.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCI IRQ mapping registers, C00h-C01h. */
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OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
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Field(PRQM, ByteAcc, NoLock, Preserve) {
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PRQI, 0x00000008,
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PRQD, 0x00000008, /* Offset: 1h */
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}
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/*
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* All PIC indexes are prefixed with P.
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* All IO-APIC indexes are prefixed with I.
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*/
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IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PIRA, 0x00000008, /* Index 0: INTA */
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PIRB, 0x00000008, /* Index 1: INTB */
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PIRC, 0x00000008, /* Index 2: INTC */
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PIRD, 0x00000008, /* Index 3: INTD */
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PIRE, 0x00000008, /* Index 4: INTE */
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PIRF, 0x00000008, /* Index 5: INTF */
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PIRG, 0x00000008, /* Index 6: INTG */
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PIRH, 0x00000008, /* Index 7: INTH */
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Offset (0x10),
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PSCI, 0x00000008, /* Index 0x10: SCI */
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PSB0, 0x00000008, /* Index 0x11: SMBUS0 */
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PASF, 0x00000008, /* Index 0x12: ASF */
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Offset (0x16),
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PPMN, 0x00000008, /* Index 0x16: PerMon */
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Offset (0x1a),
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PSIO, 0x00000008, /* Index 0x1A: SDIO */
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Offset (0x50),
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PGP0, 0x00000008, /* Index 0x50: GPP0 */
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PGP1, 0x00000008, /* Index 0x51: GPP1 */
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PGP2, 0x00000008, /* Index 0x52: GPP2 */
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PGP3, 0x00000008, /* Index 0x53: GPP3 */
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Offset (0x62),
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PGPI, 0x00000008, /* Index 0x62: GPIO */
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Offset (0x70),
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PI20, 0x00000008, /* Index 0x70: I2C0/I3C0 */
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PI21, 0x00000008, /* Index 0x71: I2C1/I3C1 */
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PI22, 0x00000008, /* Index 0x72: I2C2/I3C2 */
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PI23, 0x00000008, /* Index 0x73: I2C3/I3C3 */
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PUA0, 0x00000008, /* Index 0x74: UART0 */
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PUA1, 0x00000008, /* Index 0x75: UART1 */
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PI24, 0x00000008, /* Index 0x76: I2C4 */
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PI25, 0x00000008, /* Index 0x77: I2C5 */
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PUA2, 0x00000008, /* Index 0x78: UART2 */
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PUA3, 0x00000008, /* Index 0x79: UART3 */
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/* IO-APIC IRQs */
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Offset (0x80),
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IORA, 0x00000008, /* Index 0x80: INTA */
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IORB, 0x00000008, /* Index 0x81: INTB */
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IORC, 0x00000008, /* Index 0x82: INTC */
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IORD, 0x00000008, /* Index 0x83: INTD */
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IORE, 0x00000008, /* Index 0x84: INTE */
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IORF, 0x00000008, /* Index 0x85: INTF */
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IORG, 0x00000008, /* Index 0x86: INTG */
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IORH, 0x00000008, /* Index 0x87: INTH */
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Offset (0x90),
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ISCI, 0x00000008, /* Index 0x90: SCI */
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ISB0, 0x00000008, /* Index 0x91: SMBUS0 */
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IASF, 0x00000008, /* Index 0x92: ASF */
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Offset (0x96),
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IPMN, 0x00000008, /* Index 0x96: PerMon */
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Offset (0x9a),
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ISIO, 0x00000008, /* Index 0x9A: SDIO */
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Offset (0xD0),
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IGP0, 0x00000008, /* Index 0xD0: GPP0 */
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IGP1, 0x00000008, /* Index 0xD1: GPP1 */
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IGP2, 0x00000008, /* Index 0xD2: GPP2 */
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IGP3, 0x00000008, /* Index 0xD3: GPP3 */
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Offset (0xE2),
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IGPI, 0x00000008, /* Index 0xE2: GPIO */
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Offset (0xF0),
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II20, 0x00000008, /* Index 0xF0: I2C0/I3C0 */
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II21, 0x00000008, /* Index 0xF1: I2C1/I3C1 */
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II22, 0x00000008, /* Index 0xF2: I2C2/I3C2 */
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II23, 0x00000008, /* Index 0xF3: I2C3/I3C3 */
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IUA0, 0x00000008, /* Index 0xF4: UART0 */
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IUA1, 0x00000008, /* Index 0xF5: UART1 */
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II24, 0x00000008, /* Index 0xF6: I2C4 */
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II25, 0x00000008, /* Index 0xF7: I2C5 */
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IUA2, 0x00000008, /* Index 0xF8: UART2 */
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IUA3, 0x00000008, /* Index 0xF9: UART3 */
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}
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6
src/soc/amd/genoa/acpi/soc.asl
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6
src/soc/amd/genoa/acpi/soc.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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Scope(\_SB) {
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/* global utility methods expected within the \_SB scope */
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#include "pci_int_defs.asl"
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} /* End \_SB scope */
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56
src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
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src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_GENOA_AMD_PCI_INT_DEFS_H
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#define AMD_GENOA_AMD_PCI_INT_DEFS_H
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/*
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* * PIRQ and device routing - these define the index into the
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* * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
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* */
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#define PIRQ_NC 0x1f /* Not Used */
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#define PIRQ_A 0x00 /* INT A */
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#define PIRQ_B 0x01 /* INT B */
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#define PIRQ_C 0x02 /* INT C */
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#define PIRQ_D 0x03 /* INT D */
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#define PIRQ_E 0x04 /* INT E */
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#define PIRQ_F 0x05 /* INT F */
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#define PIRQ_G 0x06 /* INT G */
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#define PIRQ_H 0x07 /* INT H */
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#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
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#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
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#define PIRQ_HPET_L 0x0a /* Miscellaneous1 IRQ Settings */
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#define PIRQ_HPET_H 0x0b /* Miscellaneous2 IRQ Settings */
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#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
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#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
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#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
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#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
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#define PIRQ_SCI 0x10 /* SCI IRQ */
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#define PIRQ_SMBUS 0x11 /* SMBUS0 */
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#define PIRQ_ASF 0x12 /* ASF */
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/* 0x13-0x15 reserved */
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#define PIRQ_PMON 0x16 /* Performance Monitor */
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/* 0x17-0x19 reserved */
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#define PIRQ_SDIO 0x1a /* SDIO */
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/* 0x1b-0x49 reserved */
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#define PIRQ_GPP0 0x50 /* GPPInt0 */
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#define PIRQ_GPP1 0x51 /* GPPInt1 */
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#define PIRQ_GPP2 0x52 /* GPPInt2 */
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#define PIRQ_GPP3 0x53 /* GPPInt3 */
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/* 0x54-0x59 reserved */
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#define PIRQ_SCI 0x60 /* SCI Interrupt */
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#define PIRQ_SMI 0x61 /* SMI Interrupt */
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#define PIRQ_GPIO 0x62 /* GPIO Interrupt */
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/* 0x63-0x6f reserved */
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#define PIRQ_I2C0 0x70 /* I2C0/I3C0 */
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#define PIRQ_I2C1 0x71 /* I2C1/I3C1 */
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#define PIRQ_I2C2 0x72 /* I2C2/I3C2 */
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#define PIRQ_I2C3 0x73 /* I2C3/I3C3 */
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#define PIRQ_UART0 0x74 /* UART0 */
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#define PIRQ_UART1 0x75 /* UART1 */
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#define PIRQ_I2C4 0x76 /* I2C4 */
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#define PIRQ_I2C5 0x77 /* I2C5 */
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#define PIRQ_UART2 0x78 /* UART2 */
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#define PIRQ_UART3 0x79 /* UART3 */
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#endif /* AMD_GENOA_AMD_PCI_INT_DEFS_H */
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