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soc/intel/apollolake: Switch to snake case for PmicVdd2Voltage

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For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicVdd2Voltage'.

Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75857
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer
2023-06-15 14:36:09 +02:00
committed by Jakub Czapiga
parent 8c822189bd
commit 53ad07a1ec
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/apollolake/chip.c
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@@ -622,7 +622,7 @@ static void glk_fsp_silicon_init_params_cb(
/* /*
* Options to adjust PMIC Vdd2 voltage. * Options to adjust PMIC Vdd2 voltage.
*/ */
silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; silconfig->PmicVdd2Voltage = cfg->pmic_vdd2_voltage;
/* FSP should let coreboot set subsystem IDs, which are read/write-once */ /* FSP should let coreboot set subsystem IDs, which are read/write-once */
silconfig->SiSVID = 0; silconfig->SiSVID = 0;

2
src/soc/intel/apollolake/chip.h
View File

@@ -204,7 +204,7 @@ struct soc_intel_apollolake_config {
* + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
*/ */
uint32_t PmicVdd2Voltage; uint32_t pmic_vdd2_voltage;
/* Option to enable VTD feature. Default is 0 which disables VTD /* Option to enable VTD feature. Default is 0 which disables VTD
* capability in FSP. Setting this option to 1 in devicetree will enable * capability in FSP. Setting this option to 1 in devicetree will enable