sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drop some unused files and fix warnings on i945 based systems.

Browse Source 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-03-22 11:50:52 +00:00
committed by Stefan Reinauer
parent c02b4fc9db
commit 53b0ea4bf2
40 changed files with 76 additions and 311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/Kconfig
View File

@ -10,11 +10,9 @@ config USE_DCACHE_RAM
config DCACHE_RAM_BASE
hex
default 0xffdf8000 if CPU_INTEL_CORE
config DCACHE_RAM_SIZE
hex
default 0x8000 if CPU_INTEL_CORE
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex

6
src/cpu/intel/model_106cx/cache_as_ram_disable.c
View File

@ -19,6 +19,10 @@
#include "cpu/x86/car/copy_and_run.c"
/* called from assembler code */
void stage1_main(unsigned long bist);
/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@ -39,8 +43,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
}
cpu_reset_x:
printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
if(cpu_reset == 0) {

6
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@ -21,6 +21,10 @@
#include "cpu/x86/car/copy_and_run.c"
/* called from assembler code */
void stage1_main(unsigned long bist);
/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@ -40,8 +44,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
#endif
cpu_reset_x:
printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
printk(BIOS_SPEW, "No cache as ram now - ");