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intel/haswell: Use smm_subregion()

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Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-15 11:20:18 +03:00
parent abddb1fff0
commit 540151f115
2 changed files with 17 additions and 48 deletions
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15
src/northbridge/intel/haswell/memmap.c
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@@ -20,9 +20,9 @@
#include <console/console.h>
#include <commonlib/helpers.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/pci_ops.h>
#include <cbmem.h>
#include <stage_cache.h>
#include "haswell.h"
static uintptr_t smm_region_start(void)
@@ -40,17 +40,10 @@ void *cbmem_top(void)
return (void *)smm_region_start();
}
/* Region of SMM space is reserved for multipurpose use. It falls below
* the IED region and above the SMM handler. */
#define RESERVED_SMM_OFFSET \
(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE)
void stage_cache_external_region(void **base, size_t *size)
void smm_region(uintptr_t *start, size_t *size)
{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of RAM is defined to be the TSEG base address. */
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
*start = smm_region_start();
*size = CONFIG_SMM_TSEG_SIZE;
}
void fill_postcar_frame(struct postcar_frame *pcf)