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printf: Automatically prefix %p with 0x

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According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.

How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.

Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
This commit is contained in:
Julius Werner
2019-12-09 13:03:29 -08:00
committed by Patrick Georgi
parent 86da00db89
commit 540a98001d
52 changed files with 92 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/drivers/intel/fsp1_1/fsp_util.c
View File

@@ -102,22 +102,22 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
(u8)(fsp_header->ImageRevision & 0xff));
#if CONFIG(DISPLAY_FSP_ENTRY_POINTS)
printk(BIOS_SPEW, "FSP Entry Points:\n");
printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " 0x%p: TempRamInit\n",
printk(BIOS_SPEW, " %p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " %p: TempRamInit\n",
&fsp_base[fsp_header->TempRamInitEntryOffset]);
printk(BIOS_SPEW, " 0x%p: FspInit\n",
printk(BIOS_SPEW, " %p: FspInit\n",
&fsp_base[fsp_header->FspInitEntryOffset]);
if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
printk(BIOS_SPEW, " 0x%p: MemoryInit\n",
printk(BIOS_SPEW, " %p: MemoryInit\n",
&fsp_base[fsp_header->FspMemoryInitEntryOffset]);
printk(BIOS_SPEW, " 0x%p: TempRamExit\n",
printk(BIOS_SPEW, " %p: TempRamExit\n",
&fsp_base[fsp_header->TempRamExitEntryOffset]);
printk(BIOS_SPEW, " 0x%p: SiliconInit\n",
printk(BIOS_SPEW, " %p: SiliconInit\n",
&fsp_base[fsp_header->FspSiliconInitEntryOffset]);
}
printk(BIOS_SPEW, " 0x%p: NotifyPhase\n",
printk(BIOS_SPEW, " %p: NotifyPhase\n",
&fsp_base[fsp_header->NotifyPhaseEntryOffset]);
printk(BIOS_SPEW, " 0x%p: Image End\n",
printk(BIOS_SPEW, " %p: Image End\n",
&fsp_base[fsp_header->ImageSize]);
#endif
}

2
src/drivers/intel/fsp1_1/hob.c
View File

@@ -282,7 +282,7 @@ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
* the end of the HOB list
*/
printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr);
printk(BIOS_DEBUG, "%p: hob_list_ptr\n", hob_list_ptr);
do {
EFI_HOB_GENERIC_HEADER *current_header_ptr =
(EFI_HOB_GENERIC_HEADER *)current_hob;

16
src/drivers/intel/fsp1_1/raminit.c
View File

@@ -66,10 +66,10 @@ void raminit(struct romstage_params *params)
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
printk(BIOS_DEBUG, "VPD Data: %p\n", vpd_ptr);
upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
fsp_header->ImageBase);
printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
printk(BIOS_DEBUG, "UPD Data: %p\n", upd_ptr);
original_params = (void *)((u8 *)upd_ptr +
upd_ptr->MemoryInitUpdOffset);
memcpy(&memory_init_params, original_params,
@@ -110,12 +110,12 @@ void raminit(struct romstage_params *params)
/* Call FspMemoryInit to initialize RAM */
fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
+ fsp_header->FspMemoryInitEntryOffset);
printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
printk(BIOS_DEBUG, "Calling FspMemoryInit: %p\n", fsp_memory_init);
printk(BIOS_SPEW, " %p: NvsBufferPtr\n",
fsp_memory_init_params.NvsBufferPtr);
printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
printk(BIOS_SPEW, " %p: RtBufferPtr\n",
fsp_memory_init_params.RtBufferPtr);
printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
printk(BIOS_SPEW, " %p: HobListPtr\n",
fsp_memory_init_params.HobListPtr);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
@@ -151,7 +151,7 @@ void raminit(struct romstage_params *params)
}
/* Migrate CAR data */
printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
printk(BIOS_DEBUG, "%p: cbmem_top\n", cbmem_top());
if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes);
@@ -216,7 +216,7 @@ void raminit(struct romstage_params *params)
/* Get the address of the CBMEM region for the FSP reserved memory */
fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
printk(BIOS_DEBUG, "%p: fsp_reserved_memory_area\n",
fsp_reserved_memory_area);
/* Verify the order of CBMEM root and FSP memory */

6
src/drivers/intel/fsp1_1/ramstage.c
View File

@@ -81,10 +81,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
/* Initialize the UPD values */
vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
printk(BIOS_DEBUG, "%p: VPD Data\n", vpd_ptr);
upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
printk(BIOS_DEBUG, "%p: UPD Data\n", upd_ptr);
original_params = (void *)((u8 *)upd_ptr +
upd_ptr->SiliconInitUpdOffset);
memcpy(&silicon_init_params, original_params,
@@ -114,7 +114,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ fsp_info_header->FspSiliconInitEntryOffset);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n",
&silicon_init_params, fsp_silicon_init);
post_code(POST_FSP_SILICON_INIT);
status = fsp_silicon_init(&silicon_init_params);

2
src/drivers/intel/fsp1_1/romstage.c
View File

@@ -220,7 +220,7 @@ __weak void mainboard_save_dimm_info(
* table 17
*/
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info);
if (mem_info == NULL)
return;
memset(mem_info, 0, sizeof(*mem_info));

14
src/drivers/intel/fsp2_0/debug.c
View File

@@ -40,9 +40,9 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
/* Display the call entry point and parameters */
if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
return;
printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init);
printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd);
printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", fsp_get_hob_list_ptr());
printk(BIOS_SPEW, "Calling FspMemoryInit: %p\n", memory_init);
printk(BIOS_SPEW, "\t%p: raminit_upd\n", fspm_new_upd);
printk(BIOS_SPEW, "\t%p: &hob_list_ptr\n", fsp_get_hob_list_ptr());
}
void fsp_debug_after_memory_init(uint32_t status)
@@ -83,8 +83,8 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
/* Display the call to FSP SiliconInit */
if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
return;
printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init);
printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd);
printk(BIOS_SPEW, "Calling FspSiliconInit: %p\n", silicon_init);
printk(BIOS_SPEW, "\t%p: upd\n", fsps_new_upd);
}
void fsp_debug_after_silicon_init(uint32_t status)
@@ -111,8 +111,8 @@ void fsp_before_debug_notify(fsp_notify_fn notify,
return;
printk(BIOS_SPEW, "0x%08x: notify_params->phase\n",
notify_params->phase);
printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify);
printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params);
printk(BIOS_SPEW, "Calling FspNotify: %p\n", notify);
printk(BIOS_SPEW, "\t%p: notify_params\n", notify_params);
}
void fsp_debug_after_notify(uint32_t status)

4
src/drivers/intel/fsp2_0/hob_display.c
View File

@@ -186,12 +186,12 @@ void fsp_display_hobs(void)
/* Display the HOB list pointer */
printk(BIOS_SPEW, "\n=== FSP HOBs ===\n");
printk(BIOS_SPEW, "0x%p: hob_list_ptr\n", hob);
printk(BIOS_SPEW, "%p: hob_list_ptr\n", hob);
/* Walk the list of HOBs */
while (1) {
/* Display the HOB header */
printk(BIOS_SPEW, "0x%p, 0x%08x bytes: %s\n", hob, hob->length,
printk(BIOS_SPEW, "%p, 0x%08x bytes: %s\n", hob, hob->length,
fsp_get_hob_type_name(hob));
switch (hob->type) {
default:

2
src/drivers/intel/fsp2_0/hob_verify.c
View File

@@ -56,7 +56,7 @@ void fsp_verify_memory_init_hobs(void)
}
if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n",
printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
range_entry_end(&tolum), cbmem_top());
die("Space between cbmem_top and BIOS TOLUM!\n");
}

2
src/drivers/intel/fsp2_0/temp_ram_exit.c
View File

@@ -40,7 +40,7 @@ void fsp_temp_ram_exit(void)
die("Invalid FSPM header!\n");
temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry);
printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit);
printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit);
status = temp_ram_exit(NULL);
if (status != FSP_SUCCESS) {

2
src/drivers/intel/fsp2_0/upd_display.c
View File

@@ -32,7 +32,7 @@ static void fspm_display_arch_params(const FSPM_ARCH_UPD *old,
const FSPM_ARCH_UPD *new)
{
/* Display the architectural parameters for MemoryInit */
printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",
printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: %p\n",
new);
fsp_display_upd_value("Revision", sizeof(old->Revision),
old->Revision, new->Revision);