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- Changes to the pci config routines moving them closer to the non romcc API

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The goal is to have the same interface with or without romcc.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-06-12 17:55:54 +00:00
parent 05f26fcb57
commit 540ae01cd3
7 changed files with 123 additions and 106 deletions
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12
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@@ -11,16 +11,16 @@
static void enable_smbus(void)
{
uint32_t addr;
addr = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
if (addr == ~0U) {
device_t dev;
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n");
}
uint8_t enable;
print_debug("SMBus controller enabled\r\n");
pci_write_config32(addr + 0x58, SMBUS_IO_BASE | 1);
enable = pci_read_config8(addr + 0x41);
pci_write_config8(addr + 0x41, enable | (1 << 7));
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
enable = pci_read_config8(dev, 0x41);
pci_write_config8(dev, 0x41, enable | (1 << 7));
}

9
src/southbridge/amd/amd8111/amd8111_enable_rom.c
View File

@@ -2,17 +2,14 @@
static void amd8111_enable_rom(void)
{
unsigned char byte;
uint32_t addr;
device_t addr;
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
/* Locate the amd8111 */
addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
/* Refine the address to point at the rom enable byte */
addr += 0x43;
/* Set the 4MB enable bit bit */
byte = pci_read_config8(addr);
byte = pci_read_config8(addr, 0x43);
byte |= 0x80;
pci_write_config8(addr, byte);
pci_write_config8(addr, 0x43, byte);
}