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arch/x86: Add postcar_frame_common_mtrrs()

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As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.

Add possibility for the platform to skip these if
required.

Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-09 11:41:15 +03:00
parent 5bc641afeb
commit 544878b563
15 changed files with 24 additions and 74 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/x86/include/arch/cpu.h
View File

@@ -302,6 +302,7 @@ struct postcar_frame {
uint32_t upper_mask;
int max_var_mtrrs;
int num_var_mtrrs;
int skip_common_mtrr;
};
/*
@@ -322,6 +323,11 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
*/
void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
/*
* Add a common MTRR setup most platforms will have as a subset.
*/
void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
/*
* Push used MTRR and Max MTRRs on to the stack
* and return pointer to stack top.

12
src/arch/x86/postcar_loader.c
View File

@@ -120,6 +120,18 @@ void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
{
if (pcf->skip_common_mtrr)
return;
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
}
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
{
/*