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Intel cpus: Extend cache to cover complete Flash Device

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CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
would not cover the bottom 4 MB when ramstage is decompressed.

Verify CACHE_ROM_SIZE is power of two.
One may set CACHE_ROM_SIZE==0 to disable this cache.

Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1146
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
This commit is contained in:
Kyösti Mälkki
2012-06-30 11:41:08 +03:00
committed by Sven Schnelle
parent ae7d6ef8b7
commit 5458b9d90a
4 changed files with 17 additions and 8 deletions
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6
src/include/cpu/x86/mtrr.h
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@@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void);
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0)
# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
#endif
#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12)
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif