Replace hlt with halt()

There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.

All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).

Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/arch/arm/armv4/bootblock_simple.c

@@ -20,11 +20,11 @@
  */
 
 #include <arch/exception.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 
 void main(void)
 {
@@ -42,5 +42,5 @@ void main(void)
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }

src/arch/arm/armv7/bootblock_simple.c

@@ -21,11 +21,11 @@
 
 #include <arch/cache.h>
 #include <arch/exception.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <bootblock_common.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 #include <smp/node.h>
 
 void main(void)
@@ -44,5 +44,5 @@ void main(void)
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }

src/arch/arm64/armv8/bootblock_simple.c

@@ -21,11 +21,11 @@
 
 #include <bootblock_common.h>
 #include <arch/cache.h>
-#include <arch/hlt.h>
 #include <arch/stages.h>
 #include <arch/exception.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <halt.h>
 
 static int boot_cpu(void)
 {
@@ -69,5 +69,5 @@ void main(void)
 	printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry);
 
 	if (entry) stage_exit(entry);
-	hlt();
+	halt();
 }

src/arch/x86/init/bootblock_normal.c

@@ -1,6 +1,7 @@
 #include <smp/node.h>
 #include <bootblock_common.h>
 #include <pc80/mc146818rtc.h>
+#include <halt.h>
 
 static const char *get_fallback(const char *stagelist) {
 	while (*stagelist) stagelist++;
@@ -47,5 +48,5 @@ static void main(unsigned long bist)
 	if (entry) call(entry, bist);
 
 	/* duh. we're stuck */
-	asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+	halt();
 }

src/arch/x86/init/bootblock_simple.c

@@ -1,5 +1,6 @@
 #include <smp/node.h>
 #include <bootblock_common.h>
+#include <halt.h>
 
 static void main(unsigned long bist)
 {
@@ -18,5 +19,5 @@ static void main(unsigned long bist)
 	unsigned long entry;
 	entry = findstage(target1);
 	if (entry) call(entry, bist);
-	asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+	halt();
 }

src/cpu/intel/haswell/bootblock.c

@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
@@ -106,9 +107,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	while (1) {
+	halt();
-		asm("hlt");
-	}
 }
 
 static void check_for_clean_reset(void)
@@ -122,9 +121,7 @@ static void check_for_clean_reset(void)
 	if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
 		outb(0x0, 0xcf9);
 		outb(0x6, 0xcf9);
-		while (1) {
+		halt();
-			asm("hlt");
-		}
 	}
 }
 

src/cpu/intel/model_2065x/bootblock.c

@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 
@@ -109,7 +110,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	asm("hlt");
+	halt();
 }
 
 static void bootblock_cpu_init(void)

src/cpu/intel/model_206ax/bootblock.c

@@ -23,6 +23,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
+#include <halt.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
@@ -110,7 +111,7 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);
-	asm("hlt");
+	halt();
 }
 
 static void bootblock_cpu_init(void)

src/ec/google/chromeec/ec.c

@@ -23,7 +23,7 @@
 #include <bootmode.h>
 #include <arch/io.h>
 #include <delay.h>
-#include <arch/hlt.h>
+#include <halt.h>
 #include <reset.h>
 #include <elog.h>
 #include <stdlib.h>
@@ -125,7 +125,7 @@ void google_chromeec_check_ec_image(int expected_type)
 		google_chromeec_command(&cec_cmd);
 		udelay(1000);
 		hard_reset();
-		hlt();
+		halt();
 	}
 }
 
@@ -447,7 +447,7 @@ void google_chromeec_init(void)
 		google_chromeec_command(&cec_cmd);
 		udelay(1000);
 		hard_reset();
-		hlt();
+		halt();
 	}
 
 }

src/mainboard/a-trend/atc-6220/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/a-trend/atc-6240/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"

src/mainboard/aaeon/pfm-540i_revb/romstage.c

@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"

src/mainboard/advantech/pcm-5820/romstage.c

@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"

src/mainboard/amd/db800/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/amd/norwich/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/amd/rumba/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>

src/mainboard/apple/macbook21/romstage.c

@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -313,8 +314,7 @@ void main(unsigned long bist)
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");
 		outb(0x6, 0xcf9);
-		while (1)
+		halt();
-			asm("hlt");
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/artecgroup/dbe61/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"

src/mainboard/asi/mb_5blgp/romstage.c

@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"

src/mainboard/asi/mb_5blmp/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/early_serial.c"

src/mainboard/asus/mew-am/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/asus/mew-vm/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "superio/smsc/lpc47b272/early_serial.c"

src/mainboard/asus/p2b-d/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/asus/p2b-ds/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/asus/p2b-f/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/asus/p2b-ls/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/asus/p2b/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/asus/p3b-f/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/axus/tc320/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"

src/mainboard/azza/pt-6ibd/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/bachmann/ot200/romstage.c

@@ -25,7 +25,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/bcom/winnet100/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"

src/mainboard/bcom/winnetp680/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"

src/mainboard/bifferos/bifferboard/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>

src/mainboard/biostar/m6tba/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/compaq/deskpro_en_sff_p600/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <lib.h>
 #include "drivers/pc80/udelay_io.c"

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/eaglelion/5bcm/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "superio/nsc/pc97317/early_serial.c"

src/mainboard/ecs/p6iwp-fe/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/emulation/qemu-i440fx/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>

src/mainboard/emulation/qemu-q35/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>

src/mainboard/getac/p470/romstage.c

@@ -31,6 +31,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -292,7 +293,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/gigabyte/ga-6bxc/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/gigabyte/ga-6bxe/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/hp/e_vectra_p2706t/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 /* TODO: It's a PC87364 actually! */

src/mainboard/ibase/mb899/romstage.c

@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
@@ -243,7 +244,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/iei/juki-511p/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977f/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"

src/mainboard/iei/nova4899r/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "superio/winbond/w83977tf/early_serial.c"
 #include "southbridge/amd/cs5530/enable_rom.c"

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/iei/pm-lx-800-r11/romstage.c

@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <spd.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>

src/mainboard/iei/pm-lx2-800-r10/romstage.c

@@ -23,7 +23,6 @@
 #include <stdlib.h>
 #include <spd.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>

src/mainboard/intel/d810e2cb/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801bx/i82801bx.h"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/jetway/j7f2/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"

src/mainboard/kontron/986lcd-m/romstage.c

@@ -32,6 +32,7 @@
 #include "option_table.h"
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
@@ -354,7 +355,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/lanner/em8510/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <lib.h>
 #include <spd.h>

src/mainboard/lenovo/t60/romstage.c

@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -253,7 +254,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/lenovo/x60/romstage.c

@@ -35,6 +35,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -253,8 +254,7 @@ void main(unsigned long bist)
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");
 		outb(0x6, 0xcf9);
-		while (1)
+		halt();
-			asm("hlt");
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/lippert/frontrunner/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/lippert/literunner-lx/romstage.c

@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -26,7 +26,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/mitac/6513wu/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801ax/i82801ax.h"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/msi/ms6119/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"

src/mainboard/msi/ms6147/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"

src/mainboard/msi/ms6156/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"

src/mainboard/msi/ms6178/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/nec/powermate2000/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>

src/mainboard/nokia/ip530/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/pcengines/alix1c/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"

src/mainboard/pcengines/alix2d/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"

src/mainboard/rca/rm4100/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "drivers/pc80/udelay_io.c"
 #include <console/console.h>
 #include <lib.h>

src/mainboard/roda/rk886ex/romstage.c

@@ -33,6 +33,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
+#include <halt.h>
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -276,7 +277,7 @@ void main(unsigned long bist)
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		halt();
 	}
 
 	/* Perform some early chipset initialization required

src/mainboard/soyo/sy-6ba-plus-iii/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/technologic/ts5300/romstage.c

@@ -8,7 +8,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"

src/mainboard/televideo/tc7020/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/early_serial.c"

src/mainboard/thomson/ip1000/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "drivers/pc80/udelay_io.c"
 #include <console/console.h>
 #include <lib.h>

src/mainboard/traverse/geos/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"

src/mainboard/tyan/s1846/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/via/epia-cn/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/cn700/raminit.h"

src/mainboard/via/epia-m/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "northbridge/via/vt8623/raminit.h"

src/mainboard/via/epia-m700/romstage.c

@@ -30,7 +30,6 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/vx800/vx800.h"

src/mainboard/via/epia-m850/romstage.c

@@ -26,7 +26,6 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/io.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include <cpu/x86/bist.h>

src/mainboard/via/epia-n/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/via/epia/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include "northbridge/via/vt8601/raminit.h"

src/mainboard/via/pc2500e/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>

src/mainboard/via/vt8454c/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "northbridge/via/cx700/raminit.h"

src/mainboard/winent/pl6064/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"

src/mainboard/wyse/s50/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include <console/console.h>
 #include <lib.h>
 #include "cpu/x86/bist.h"

src/northbridge/intel/gm45/early_reset.c

@@ -21,6 +21,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <halt.h>
 #include "gm45.h"
 
 void gm45_early_reset(void/*const timings_t *const timings*/)
@@ -69,5 +70,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
 	/* Perform system reset through CF9 interface. */
 	outb(0x02, 0xcf9); /* Set system reset bit. */
 	outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
-	while (1) asm("hlt");
+	halt();
 }

src/northbridge/intel/i5000/raminit.c

@@ -26,6 +26,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <console/console.h>
+#include <halt.h>
 #include <spd.h>
 #include <types.h>
 #include <string.h>
@@ -1522,7 +1523,7 @@ static void i5000_try_restart(const char *msg)
 	printk(BIOS_INFO, "%s", msg);
 	i5000_dump_error_registers();
 	outb(0x06, 0xcf9);
-	for(;;) asm volatile("hlt");
+	halt();
 }
 
 static void i5000_pam_setup(void)
@@ -1624,7 +1625,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
 		pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
 		/* FSB:FBD mapping changed, needs hard reset */
 		outb(0x06, 0xcf9);
-		for(;;) asm volatile("hlt");
+		halt();
 	}
 	return 0;
 }

src/northbridge/intel/i945/early_init.c

@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <cbmem.h>
+#include <halt.h>
 #include <string.h>
 #include "i945.h"
 
@@ -512,7 +513,7 @@ static void i945_setup_dmi_rcrb(void)
 			reg32 |= (3 << 0);
 			DMIBAR32(0x224) = reg32;
 			outb(0x06, 0xcf9);
-			for (;;) asm("hlt");	/* wait for reset */
+			halt(); /* wait for reset */
 		}
 	}
 }

src/northbridge/intel/i945/raminit.c

@@ -24,6 +24,7 @@
 #include <spd.h>
 #include <string.h>
 #include <arch/io.h>
+#include <halt.h>
 #include <lib.h>
 #include "raminit.h"
 #include "i945.h"
@@ -281,7 +282,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
 			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
-			for (;;) asm("hlt"); /* Wait for reset! */
+			halt(); /* Wait for reset! */
 		}
 	}
 
@@ -311,7 +312,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
 		printk(BIOS_DEBUG, "Reset required.\n");
 		outb(0x00, 0xcf9);
 		outb(0x0e, 0xcf9);
-		for (;;) asm("hlt"); /* Wait for reset! */
+		halt(); /* Wait for reset! */
 	}
 }
 

src/northbridge/intel/nehalem/raminit.c

@@ -28,7 +28,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
@@ -38,6 +37,7 @@
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
 #include <arch/cpu.h>
+#include <halt.h>
 #include <spd.h>
 #include "raminit.h"
 #include <timestamp.h>
@@ -3805,9 +3805,7 @@ void chipset_init(const int s3resume)
 		write_mchbar8(0x2ca8, 0);
 		outb(0x6, 0xcf9);
 #if REAL
-		while (1) {
+		halt();
-			asm volatile ("hlt");
-		}
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4041,9 +4039,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 			       "Interrupted RAM init, reset required.\n");
 			outb(0x6, 0xcf9);
 #if REAL
-			while (1) {
+			halt();
-				asm volatile ("hlt");
-			}
 #endif
 		}
 	}
@@ -4407,9 +4403,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 		write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);
 		write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);
 #if REAL
-		while (1) {
+		halt();
-			asm volatile ("hlt");
-		}
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4510,9 +4504,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 			outb(0xe, 0xcf9);
 
 #if REAL
-			while (1) {
+			halt();
-				asm volatile ("hlt");
-			}
 #else
 			printf("CP5\n");
 			exit(0);
@@ -4990,7 +4982,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0xe, 0xcf9);
-		hlt();
+		halt();
 	}
 #endif
 }

src/northbridge/intel/sandybridge/raminit.c

@@ -21,7 +21,6 @@
 #include <console/usb.h>
 #include <bootmode.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
@@ -29,6 +28,7 @@
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
+#include <halt.h>
 #include "raminit.h"
 #include "pei_data.h"
 #include "sandybridge.h"
@@ -239,7 +239,7 @@ void sdram_initialize(struct pei_data *pei_data)
 	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
 		printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Pass console handler in pei_data */

src/northbridge/via/vx800/examples/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/hlt.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "northbridge/via/vx800/vx800.h"

src/soc/intel/baytrail/smihandler.c

@@ -19,13 +19,13 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <elog.h>
+#include <halt.h>
 
 #include <baytrail/pci_devs.h>
 #include <baytrail/pmc.h>
@@ -161,7 +161,7 @@ static void southbridge_smi_sleep(void)
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
 	if (slp_typ > 1)
-		hlt();
+		halt();
 
 	/* In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake