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Revert "soc/amd/cezanne: Add support to perform early EC sync"

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This reverts commit ad7c33abd2. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.

BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.

Cq-Depend: chromium:2832032
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I34f8433739754365c8e5a10fdf7e58e3d1e7e797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52419
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2021-04-16 11:24:33 -06:00
committed by Patrick Georgi
parent 9605136bc6
commit 54888e8d7d
1 changed files with 0 additions and 4 deletions
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4
src/soc/amd/cezanne/romstage.c
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@@ -9,16 +9,12 @@
#include <console/console.h> #include <console/console.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <program_loading.h> #include <program_loading.h>
#include <security/vboot/vboot_common.h>
asmlinkage void car_stage_entry(void) asmlinkage void car_stage_entry(void)
{ {
post_code(0x40); post_code(0x40);
console_init(); console_init();
if (CONFIG(VBOOT_EARLY_EC_SYNC))
vboot_sync_ec();
post_code(0x41); post_code(0x41);
/* Snapshot chipset state prior to any FSP call */ /* Snapshot chipset state prior to any FSP call */