Drop some duplicates of PCI-e config functions

These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.

Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/southbridge/intel/bd82x6x/finalize.c

@@ -20,7 +20,6 @@
 
 #include <arch/io.h>
 #include <console/post_codes.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
 #include "pch.h"
 #include <spi-generic.h>
 

src/southbridge/intel/bd82x6x/me.c

@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>

src/southbridge/intel/bd82x6x/me_8.x.c

@@ -38,7 +38,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>

src/southbridge/intel/bd82x6x/smihandler.c

@@ -37,7 +37,7 @@
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value

src/southbridge/intel/bd82x6x/spi.c

@@ -34,7 +34,7 @@
 #define min(a, b) ((a)<(b)?(a):(b))
 
 #ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pcie_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\

src/southbridge/intel/i82801dx/smihandler.c

@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {

src/southbridge/intel/i82801gx/smihandler.c

@@ -207,7 +207,7 @@ static void dump_tco_status(u32 tco_sts)
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include "../../../northbridge/intel/i945/pcie_config.c"
+#include <arch/pci_mmio_cfg.h>
 
 int southbridge_io_trap_handler(int smif)
 {

src/southbridge/intel/sch/smihandler.c

@@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts)
 }
 #endif
 
-
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-//#include "../../../northbridge/intel/i945/pcie_config.c"
-
 int southbridge_io_trap_handler(int smif)
 {
 	//global_nvs_t *gnvs = (global_nvs_t *)0xc00;