Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-54
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -214,13 +214,13 @@ setupsc520(void){
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/* the 0x80 led should now be working*/
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outb(0xaa, 0x80);
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#if 0
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/* wtf are 680 leds ... */
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par = (unsigned long *) 0xfffef0c4;
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*par = 0x28000680;
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/* well? */
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outb(0x55, 0x80);
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#endif
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/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
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cp = (unsigned char *)0xfffefcc0;
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@ -232,7 +232,7 @@ setupsc520(void){
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cp = (unsigned char *)0x0fffefd20;
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*cp = 0x01;
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cp = (unsigned char *)0x0fffefd28;
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x cp = (unsigned char *)0x0fffefd28;
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*cp = 0x0c;
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cp = (unsigned char *)0x0fffefd29;
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@ -258,12 +258,12 @@ setupsc520(void){
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outl(0xcfc, 0x2); /*set the memory access enable bit*/
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OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
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#endif
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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#if 0
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
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*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
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*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
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@ -279,9 +279,12 @@ setupsc520(void){
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*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
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*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
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*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
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// *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
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#else
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par += 15;
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#endif
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*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
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}
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