sravan/system76-coreboot
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Change all clrsetbits_leXX() to clrsetbitsXX()

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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Julius Werner
2019-12-02 22:03:27 -08:00
committed by Patrick Georgi
parent 1c37157218
commit 55009af42c
108 changed files with 2022 additions and 2025 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/mediatek/common/ddp.c
View File

@@ -31,7 +31,7 @@ void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
void rdma_start(void)
{
setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
}
void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
@@ -39,8 +39,8 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
u32 threshold;
u32 reg;
clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width);
clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height);
clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width);
clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height);
/*
* Enable FIFO underflow since DSI and DPI can't be blocked. Set the
@@ -78,5 +78,5 @@ void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
write32(&ovl0->rdma[0].ctrl, BIT(0));
write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
setbits_le32(&ovl0->src_con, BIT(0));
setbits32(&ovl0->src_con, BIT(0));
}

8
src/soc/mediatek/common/dsi.c
View File

@@ -120,12 +120,12 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing)
static void mtk_dsi_clk_hs_mode_enable(void)
{
setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
setbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
}
static void mtk_dsi_clk_hs_mode_disable(void)
{
clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
clrbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
}
static void mtk_dsi_set_mode(u32 mode_flags)
@@ -394,8 +394,8 @@ static void mtk_dsi_send_init_commands(const u8 *buf)
static void mtk_dsi_reset_dphy(void)
{
setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
}
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,

3
src/soc/mediatek/common/gpio.c
View File

@@ -63,8 +63,7 @@ void gpio_set_mode(gpio_t gpio, int mode)
pos_bit_calc_for_mode(gpio, &pos, &bit);
clrsetbits_le32(&mtk_gpio->mode[pos].val,
mask << bit, mode << bit);
clrsetbits32(&mtk_gpio->mode[pos].val, mask << bit, mode << bit);
}
int gpio_get(gpio_t gpio)

12
src/soc/mediatek/common/mtcmos.c
View File

@@ -46,17 +46,17 @@ static void mtcmos_power_on(const struct power_domain_data *pd)
write32(&mtk_spm->poweron_config_set,
(SPM_PROJECT_CODE << 16) | (1U << 0));
setbits_le32(pd->pwr_con, PWR_ON);
setbits_le32(pd->pwr_con, PWR_ON_2ND);
setbits32(pd->pwr_con, PWR_ON);
setbits32(pd->pwr_con, PWR_ON_2ND);
while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
!(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
continue;
clrbits_le32(pd->pwr_con, PWR_CLK_DIS);
clrbits_le32(pd->pwr_con, PWR_ISO);
setbits_le32(pd->pwr_con, PWR_RST_B);
clrbits_le32(pd->pwr_con, pd->sram_pdn_mask);
clrbits32(pd->pwr_con, PWR_CLK_DIS);
clrbits32(pd->pwr_con, PWR_ISO);
setbits32(pd->pwr_con, PWR_RST_B);
clrbits32(pd->pwr_con, pd->sram_pdn_mask);
while (read32(pd->pwr_con) & pd->sram_ack_mask)
continue;

36
src/soc/mediatek/common/spi.c
View File

@@ -50,8 +50,8 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave)
static void spi_sw_reset(struct mtk_spi_regs *regs)
{
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
clrbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
}
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
@@ -77,17 +77,17 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly);
clrsetbits_le32(&regs->spi_cmd_reg,
(SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN |
SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN |
SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN |
SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN),
(SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN |
SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN));
clrsetbits32(&regs->spi_cmd_reg,
(SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN |
SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN |
SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN |
SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN),
(SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN |
SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN));
mtk_spi_set_gpio_pinmux(bus, pad_select);
clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK,
clrsetbits32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK,
pad_select);
gpio_output(slave->cs_gpio, 1);
@@ -110,7 +110,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave);
struct mtk_spi_regs *regs = mtk_slave->regs;
setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT);
setbits32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT);
mtk_slave->state = MTK_SPI_IDLE;
gpio_output(mtk_slave->cs_gpio, 0);
@@ -135,10 +135,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
else
size = MIN(*bytes_in, *bytes_out);
clrsetbits_le32(&regs->spi_cfg1_reg,
SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK,
((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
(0 << SPI_CFG1_PACKET_LOOP_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg,
SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK,
((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
(0 << SPI_CFG1_PACKET_LOOP_SHIFT));
if (*bytes_out) {
const uint8_t *outb = (const uint8_t *)out;
@@ -166,10 +166,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
}
if (mtk_slave->state == MTK_SPI_IDLE) {
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN);
mtk_slave->state = MTK_SPI_PAUSE_IDLE;
} else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) {
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN);
}
stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US);
@@ -246,7 +246,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave);
struct mtk_spi_regs *regs = mtk_slave->regs;
clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN);
clrbits32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN);
spi_sw_reset(regs);
mtk_slave->state = MTK_SPI_IDLE;

4
src/soc/mediatek/common/timer.c
View File

@@ -48,8 +48,8 @@ void init_timer(void)
timer_prepare();
/* Disable timer and clear the counter */
clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN);
setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN);
setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
/* Set clock source to system clock and set clock divider to 1 */
write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);

46
src/soc/mediatek/common/usb.c
View File

@@ -32,53 +32,53 @@ static void phy_index_power_on(int index)
if (!index) {
/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
setbits32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
/* Disable power domain ISO */
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
}
/* Switch system IP to USB mode */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
clrbits32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
if (!index)
clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
clrbits32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
/* Disable force settings */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
/* Improve Rx sensitivity */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
clrsetbits32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
setbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
clrsetbits_le32(&phy->u3phya_da.reg0,
clrsetbits32(&phy->u3phya_da.reg0,
P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
clrsetbits_le32(&phy->u3phya.phya_reg9,
clrsetbits32(&phy->u3phya.phya_reg9,
P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
if (!index)
clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
clrbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
clrsetbits_le32(&phy->u3phya.phya_reg6,
clrsetbits32(&phy->u3phya.phya_reg6,
P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
clrsetbits32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
clrsetbits32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));
clrsetbits_le32(&phy->u2phy.u2phydtm1,
clrsetbits32(&phy->u2phy.u2phydtm1,
P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
/* Set USB 2.0 slew rate value */
clrsetbits_le32(&phy->u2phy.usbphyacr5,
clrsetbits32(&phy->u2phy.usbphyacr5,
PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
/* Set USB 2.0 disconnect threshold */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
clrsetbits32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
}
@@ -128,18 +128,18 @@ static int u3phy_ports_enable(void)
u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);
/* Power on host ip */
clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
clrbits32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
/* Power on and enable all u3 ports */
for (i = 0; i < u3_port_num; i++) {
clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],
clrsetbits32(&ippc_regs->u3_ctrl_p[i],
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
CTRL_U3_PORT_HOST_SEL);
}
/* Power on and enable all u2 ports */
for (i = 0; i < u2_port_num; i++) {
clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],
clrsetbits32(&ippc_regs->u2_ctrl_p[i],
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
CTRL_U2_PORT_HOST_SEL);
}
@@ -149,8 +149,8 @@ static int u3phy_ports_enable(void)
static inline void ssusb_soft_reset(void)
{
/* Reset whole ip */
setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
setbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
}
__weak void mtk_usb_prepare(void) { /* do nothing */ }

8
src/soc/mediatek/common/wdt.c
View File

@@ -45,10 +45,10 @@ int mtk_wdt_init(void)
* ENABLE: disable watchdog on initialization.
* Setting bit EXTEN to enable watchdog output.
*/
clrsetbits_le32(&mtk_wdt->wdt_mode,
MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
clrsetbits32(&mtk_wdt->wdt_mode,
MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
return wdt_sta;
}

20
src/soc/mediatek/mt8173/ddp.c
View File

@@ -60,17 +60,17 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk)
static void disp_clock_on(void)
{
clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON |
CG_CON0_SMI_LARB0 |
CG_CON0_MUTEX_32K |
CG_CON0_DISP_OVL0 |
CG_CON0_DISP_RDMA0 |
CG_CON0_DISP_COLOR0 |
CG_CON0_DISP_UFOE |
CG_CON0_DISP_OD);
clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON |
CG_CON0_SMI_LARB0 |
CG_CON0_MUTEX_32K |
CG_CON0_DISP_OVL0 |
CG_CON0_DISP_RDMA0 |
CG_CON0_DISP_COLOR0 |
CG_CON0_DISP_UFOE |
CG_CON0_DISP_OD);
clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE |
CG_CON1_DSI0_DIGITAL);
clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE |
CG_CON1_DSI0_DIGITAL);
}
void mtk_ddp_init(void)

226
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@@ -74,17 +74,17 @@ static void mem_pll_pre_init(u32 channel)
write32(&ch[channel].ddrphy_regs->mempll05_divider, 0x1 << 27);
/* enable chip top memory clock */
setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4);
setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4);
/* disable C/A and DQ M_CK clock gating */
clrbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 |
0x1 << 1);
clrbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 |
0x1 << 1);
/* enable spm control clock */
clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 |
0x1 << 0);
clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 |
0x1 << 0);
/* enable dramc 2X mode */
setbits_le32(&ch[channel].ao_regs->ddr2ctl, 1 << 0);
setbits32(&ch[channel].ao_regs->ddr2ctl, 1 << 0);
/* select internal clock path */
write32(&ch[channel].ddrphy_regs->peri[0], 0x21 << 24 | 0x27 << 16 |
@@ -94,12 +94,12 @@ static void mem_pll_pre_init(u32 channel)
0x6 << 8 | 0x1e << 0);
/* trigger to make memory clock correct phase */
setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 |
0x1 << 7);
setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 |
0x1 << 7);
if (channel == CHANNEL_A) {
/* select memory clock sync for channel A (internal source) */
clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3);
clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3);
}
}
@@ -156,11 +156,11 @@ static void mem_pll_init_phase_sync(u32 channel)
BIT(7) | BIT(5) |
BIT(4) | BIT(0));
/* spm control clock enable */
clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0),
BIT(1));
clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0),
BIT(1));
clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1),
BIT(0));
clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1),
BIT(0));
}
static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs)
@@ -169,25 +169,25 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs)
case MEMPLL_INIT:
/* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */
clrbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT);
clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT);
break;
case MEMPLL_REF_LAG:
/* REF lag FBK, delay FBK */
clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT,
mempll->delay << MEMPLL_FB_DL_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT,
mempll->delay << MEMPLL_FB_DL_SHIFT);
break;
case MEMPLL_REF_LEAD:
/* REF lead FBK, delay REF */
clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT,
mempll->delay << MEMPLL_REF_DL_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
0x1f << MEMPLL_REF_DL_SHIFT |
0x1f << MEMPLL_FB_DL_SHIFT,
mempll->delay << MEMPLL_REF_DL_SHIFT);
};
}
@@ -250,9 +250,9 @@ static void mem_pll_phase_cali(u32 channel)
/* 1. set jitter meter count number to 1024 for mempll 2 3 4 */
for (i = 0; i < 3; i++)
clrsetbits_le32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_COUNTER_MASK,
JMETER_COUNT << JMETER_COUNTER_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_COUNTER_MASK,
JMETER_COUNT << JMETER_COUNTER_SHIFT);
while (1) {
@@ -266,8 +266,8 @@ static void mem_pll_phase_cali(u32 channel)
/* 2. enable mempll 2 3 4 jitter meter */
for (i = 0; i < 3; i++)
setbits_le32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_EN_BIT);
setbits32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_EN_BIT);
/* 3. wait for jitter meter complete */
udelay(JMETER_WAIT_DONE_US);
@@ -281,8 +281,8 @@ static void mem_pll_phase_cali(u32 channel)
/* 5. disable mempll 2 3 4 jitter meter */
for (i = 0; i < 3; i++)
clrbits_le32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_EN_BIT);
clrbits32(&ch[channel].ddrphy_regs->jmeter[i],
JMETER_EN_BIT);
/* 6. all done early break */
if (mempll[0].done && mempll[1].done && mempll[2].done)
@@ -336,58 +336,58 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
udelay(2);
/* mempll2_en -> mempll4_en -> mempll3_en */
setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
udelay(100);
/* mempll_bias_lpf_en */
setbits_le32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7);
setbits32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7);
udelay(30);
/* select mempll4 band register */
setbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26);
clrbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26);
setbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26);
clrbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26);
/* PLL ready */
/* disable mempll2_en -> mempll4_en -> mempll3_en */
clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
/* disable autok mempll2_en -> mempll4_en -> mempll3_en */
clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23);
clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23);
clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23);
clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23);
clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23);
clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23);
udelay(1);
/* mempll[2->4->3]_fb_mck_sel=1 (switch to outer loop) */
setbits_le32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25);
setbits_le32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25);
setbits_le32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25);
setbits32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25);
setbits32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25);
setbits32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25);
udelay(1);
/* enable mempll2_en -> mempll4_en -> mempll3_en */
setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0);
setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0);
}
/* mempll new power-on */
write32(&mtk_spm->poweron_config_set, 0x1 << 0 |
SPM_PROJECT_CODE << 16);
/* request mempll reset/pdn mode */
setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);
setbits32(&mtk_spm->power_on_val0, 0x1 << 27);
udelay(2);
/* unrequest mempll reset/pdn mode and wait settle */
clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);
clrbits32(&mtk_spm->power_on_val0, 0x1 << 27);
udelay(31); /* PLL ready */
@@ -628,16 +628,16 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params)
write32(&ch[channel].ao_regs->padctl7, 0x0);
/* CLKTDN, DS0TDN, DS1TDN, DS2TDN, DS3TDN */
setbits_le32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 |
setbits32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 |
0x1 << 29 |
0x1 << 27 |
0x1 << 25 |
0x1 << 1);
/* DISABLE_PERBANK_REFRESH */
clrbits_le32(&ch[channel].ao_regs->rkcfg, 0x1 << 7);
clrbits32(&ch[channel].ao_regs->rkcfg, 0x1 << 7);
/* clear R_DMREFTHD to reduce MR4 wait refresh queue time */
clrbits_le32(&ch[channel].ao_regs->conf2, 0x7 << 24);
clrbits32(&ch[channel].ao_regs->conf2, 0x7 << 24);
/* duty default value */
write32(&ch[channel].ddrphy_regs->phyclkduty, 0x1 << 28 |
@@ -645,7 +645,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params)
if (!dual_rank_set) {
/* single rank, CKE1 always off */
setbits_le32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21);
setbits32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21);
}
/* default dqs rx perbit input delay */
@@ -662,72 +662,72 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params)
void div2_phase_sync(void)
{
clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider,
clrbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider,
1 << MEMCLKENB_SHIFT);
udelay(1);
setbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider,
setbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider,
1 << MEMCLKENB_SHIFT);
}
void dramc_phy_reset(u32 channel)
{
/* reset phy */
setbits_le32(&ch[channel].ddrphy_regs->phyctl1,
setbits32(&ch[channel].ddrphy_regs->phyctl1,
1 << PHYCTL1_PHYRST_SHIFT);
/* read data counter reset */
setbits_le32(&ch[channel].ao_regs->gddr3ctl1,
setbits32(&ch[channel].ao_regs->gddr3ctl1,
1 << GDDR3CTL1_RDATRST_SHIFT);
udelay(1); /* delay 1ns */
clrbits_le32(&ch[channel].ao_regs->gddr3ctl1,
clrbits32(&ch[channel].ao_regs->gddr3ctl1,
1 << GDDR3CTL1_RDATRST_SHIFT);
clrbits_le32(&ch[channel].ddrphy_regs->phyctl1,
clrbits32(&ch[channel].ddrphy_regs->phyctl1,
1 << PHYCTL1_PHYRST_SHIFT);
}
void dramc_runtime_config(u32 channel,
const struct mt8173_sdram_params *sdram_params)
{
setbits_le32(&ch[channel].ddrphy_regs->dqsgctl,
setbits32(&ch[channel].ddrphy_regs->dqsgctl,
BIT(17)|BIT(18));
/* enable hw gating */
setbits_le32(&ch[channel].ao_regs->dqscal0,
1 << DQSCAL0_STBCALEN_SHIFT);
setbits32(&ch[channel].ao_regs->dqscal0,
1 << DQSCAL0_STBCALEN_SHIFT);
/* if frequency >1600, tCKE should >7 clk */
setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4);
setbits32(&ch[channel].ao_regs->dummy, 0x1 << 4);
if (sdram_params->dram_freq * 2 < 1600 * MHz)
die("set tCKE error in runtime config");
/* DDRPHY C/A and DQ M_CK clock gating enable */
setbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 |
setbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 |
0x1 << 1);
setbits_le32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) |
setbits32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) |
BIT(11) | BIT(10) |
BIT(9) | BIT(8) |
BIT(4) | BIT(0));
/* ZQCS_ENABLE */
if (sdram_params->emi_set.cona & 0x1) {
/* dual channel, clear ZQCSCNT */
clrbits_le32(&ch[channel].ao_regs->spcmd, 0xff << 16);
clrbits32(&ch[channel].ao_regs->spcmd, 0xff << 16);
/* set ZQCSMASK for different channels */
if (channel == CHANNEL_A) {
clrbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24);
clrbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24);
} else {
setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24);
setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24);
}
/* enable ZQCSDUAL */
setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 25);
setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 25);
} else {
/* single channel, set ZQCSCNT */
setbits_le32(&ch[channel].ao_regs->spcmd, 0x8 << 16);
setbits32(&ch[channel].ao_regs->spcmd, 0x8 << 16);
}
}
@@ -736,17 +736,17 @@ void transfer_to_spm_control(void)
u32 msk;
msk = BIT(7) | BIT(11) | BIT(15);
clrbits_le32(&mtk_apmixed->ap_pll_con3, msk);
clrbits32(&mtk_apmixed->ap_pll_con3, msk);
msk = BIT(0) | BIT(4) | BIT(8);
clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk);
clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk);
msk = BIT(0) | BIT(8);
clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk);
clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk);
msk = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24);
clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk);
clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk);
clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk);
clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk);
}
void transfer_to_reg_control(void)
@@ -754,17 +754,17 @@ void transfer_to_reg_control(void)
u32 val;
val = BIT(7) | BIT(11) | BIT(15);
setbits_le32(&mtk_apmixed->ap_pll_con3, val);
setbits32(&mtk_apmixed->ap_pll_con3, val);
val = BIT(0) | BIT(4) | BIT(8);
setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val);
setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val);
val = BIT(0) | BIT(8);
write32(&ch[CHANNEL_B].ddrphy_regs->peri[3], val);
val = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24);
setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val);
setbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val);
setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val);
setbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val);
}
u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
@@ -776,9 +776,9 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
die("Invalid loopcount of engine2!");
/* Disable Test Agent1, Test Agent2 write/read */
clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN |
CONF2_TEST2R_EN |
CONF2_TEST2W_EN);
clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN |
CONF2_TEST2R_EN |
CONF2_TEST2W_EN);
/* 1. set pattern, base address, offset address */
write32(&ch[channel].nao_regs->test2_1, test2_1);
@@ -794,49 +794,49 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
switch (testaudpat) {
case XTALK:
/* TESTAUDPAT = 0 */
clrbits_le32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
clrbits32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
/* TESTXTALKPAT = 1, select xtalk pattern
* TESTAUDMODE = 0, read only
* TESTAUDBITINV = 0, no bit inversion
*/
clrsetbits_le32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTAUDBITINV_EN |
TEST2_4_TESTAUDMODE_EN,
TEST2_4_TESTXTALKPAT_EN);
clrsetbits32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTAUDBITINV_EN |
TEST2_4_TESTAUDMODE_EN,
TEST2_4_TESTXTALKPAT_EN);
break;
case AUDIO:
/* TESTAUDPAT = 1 */
setbits_le32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
setbits32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
/* TESTXTALKPAT = 0
* TESTAUDINIT = 0x11
* TESTAUDINC = 0x0d
* TESTAUDBITINV = 1
* TESTAUDMODE = 1
*/
clrsetbits_le32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTXTALKPAT_EN |
TEST2_4_TESTAUDINIT_MASK |
TEST2_4_TESTAUDINC_MASK,
TEST2_4_TESTAUDMODE_EN |
TEST2_4_TESTAUDBITINV_EN |
0x11 << TEST2_4_TESTAUDINIT_SHIFT |
0xd << TEST2_4_TESTAUDINC_SHIFT);
clrsetbits32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTXTALKPAT_EN |
TEST2_4_TESTAUDINIT_MASK |
TEST2_4_TESTAUDINC_MASK,
TEST2_4_TESTAUDMODE_EN |
TEST2_4_TESTAUDBITINV_EN |
0x11 << TEST2_4_TESTAUDINIT_SHIFT |
0xd << TEST2_4_TESTAUDINC_SHIFT);
break;
case ISI:
/* TESTAUDPAT = 0 */
clrbits_le32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
clrbits32(&ch[channel].ao_regs->test2_3,
TEST2_3_TESTAUDPAT_EN);
/* TESTXTALKPAT = 0 */
clrbits_le32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTXTALKPAT_EN);
clrbits32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTXTALKPAT_EN);
}
/* 3. set loop number */
clrsetbits_le32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK,
log2loopcount << TEST2_3_TESTCNT_SHIFT);
clrsetbits32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK,
log2loopcount << TEST2_3_TESTCNT_SHIFT);
/* 4. enable read/write test */
if (wr == TE_OP_READ_CHECK) {
@@ -844,15 +844,15 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
/* if audio pattern, enable read only */
/* (disable write after read), */
/* AUDMODE=0x48[15]=0 */
clrbits_le32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTAUDMODE_EN);
clrbits32(&ch[channel].ao_regs->test2_4,
TEST2_4_TESTAUDMODE_EN);
}
/* enable read, 0x008[30:30] */
setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
} else if (wr == TE_OP_WRITE_READ_CHECK) {
/* enable write, 0x008[31:31] */
setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN);
setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN);
/* check "read data compare ready" bit */
do {
@@ -860,8 +860,8 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
} while ((value & (1 << TESTRPT_DM_CMP_CPT_SHIFT)) == 0);
/* Disable Test Agent2 write and enable Test Agent2 read */
clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN);
setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN);
setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
}
/* 5 check "read data compare ready" bit */
@@ -876,7 +876,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
value = read32(&ch[channel].nao_regs->cmp_err);
/* 6 disable read */
clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN);
/* return CMP_ERR result, pass: 0, failure: otherwise */
return value;

196
src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
View File

@@ -42,14 +42,14 @@ void sw_impedance_cal(u32 channel,
params->impedance_drvp << 12 | params->impedance_drvn << 8;
/* DQS and DQ */
clrsetbits_le32(&ch[channel].ao_regs->iodrv6, mask, value);
clrsetbits32(&ch[channel].ao_regs->iodrv6, mask, value);
/* CLK and CMD */
clrsetbits_le32(&ch[channel].ao_regs->drvctl1, mask, value);
clrsetbits_le32(&ch[channel].ddrphy_regs->drvctl1, mask, value);
clrsetbits32(&ch[channel].ao_regs->drvctl1, mask, value);
clrsetbits32(&ch[channel].ddrphy_regs->drvctl1, mask, value);
/* DQ_2 and CMD_2 */
clrsetbits_le32(&ch[channel].ao_regs->iodrv4, mask, value);
clrsetbits32(&ch[channel].ao_regs->iodrv4, mask, value);
/* disable impcal calibration */
clrbits_le32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT |
clrbits32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT |
1 << IMP_CALI_ENN_SHIFT |
1 << IMP_CALI_EN_SHIFT |
0xf << IMP_CALI_DRVP_SHIFT |
@@ -89,40 +89,40 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params)
/* set CA pins output delay */
for (i = 0; i < (CATRAINING_NUM - 1); i++) {
order = ca_order[channel][i];
clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]],
0xf << shift[i], ca_shift[order] << shift[i]);
clrsetbits32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]],
0xf << shift[i], ca_shift[order] << shift[i]);
}
order = ca_order[channel][9];
clrsetbits_le32(&ch[channel].ddrphy_regs->dqscal0,
0xf << DQSCAL0_RA14_SHIFT,
ca_shift[order] << DQSCAL0_RA14_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->dqscal0,
0xf << DQSCAL0_RA14_SHIFT,
ca_shift[order] << DQSCAL0_RA14_SHIFT);
/* CKE and CS delay */
ca_shift_avg32 = (u32)(ca_shift_avg8 + (CATRAINING_NUM >> 1));
ca_shift_avg32 /= (u32)CATRAINING_NUM;
/* CKEDLY */
clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[4],
0x1f << CMDDLY4_CS_SHIFT |
0x1f << CMDDLY4_CKE_SHIFT,
ca_shift_avg32 << CMDDLY4_CS_SHIFT |
ca_shift_avg32 << CMDDLY4_CKE_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->cmddly[4],
0x1f << CMDDLY4_CS_SHIFT |
0x1f << CMDDLY4_CKE_SHIFT,
ca_shift_avg32 << CMDDLY4_CS_SHIFT |
ca_shift_avg32 << CMDDLY4_CKE_SHIFT);
/* CKE1DLY */
clrsetbits_le32(&ch[channel].ao_regs->dqscal1,
0x1f << DQSCAL1_CKE1_SHIFT,
ca_shift_avg32 << DQSCAL1_CKE1_SHIFT);
clrsetbits32(&ch[channel].ao_regs->dqscal1,
0x1f << DQSCAL1_CKE1_SHIFT,
ca_shift_avg32 << DQSCAL1_CKE1_SHIFT);
/* CS1DLY */
clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1,
0xf << PADCTL1_CS1_SHIFT,
ca_shift_avg32 << PADCTL1_CS1_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->padctl1,
0xf << PADCTL1_CS1_SHIFT,
ca_shift_avg32 << PADCTL1_CS1_SHIFT);
/* set max center into clk output delay */
clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1,
0xf << PADCTL1_CLK_SHIFT,
ca_max_center << PADCTL1_CLK_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->padctl1,
0xf << PADCTL1_CLK_SHIFT,
ca_max_center << PADCTL1_CLK_SHIFT);
dramc_dbg_msg("=========================================\n");
dramc_dbg_msg(" [Channel %d] CA training\n", channel);
@@ -155,8 +155,8 @@ void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params)
write32(&ch[channel].ddrphy_regs->padctl3, value);
/* DQM */
clrsetbits_le32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT,
(value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT);
clrsetbits32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT,
(value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT);
/* DQ */
for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++) {
@@ -203,10 +203,10 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val)
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
/* Rank 0 P0/P1 coarse tune settings */
clrsetbits_le32(&ch[channel].ao_regs->dqsctl1,
0xf << DQSCTL1_DQSINCTL_SHIFT,
coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT &
0xf << DQSCTL1_DQSINCTL_SHIFT);
clrsetbits32(&ch[channel].ao_regs->dqsctl1,
0xf << DQSCTL1_DQSINCTL_SHIFT,
coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT &
0xf << DQSCTL1_DQSINCTL_SHIFT);
/* DQSINCTL does not have P1. */
/* Need to use TXDLY_DQSGATE/TXDLY_DQSGATE_P1 to set */
@@ -214,33 +214,33 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val)
selph2_dqsgate = (curr_val >> 2) - coarse_tune_start;
selph2_dqsgate_p1 = (curr_val_p1 >> 2) - coarse_tune_start;
clrsetbits_le32(&ch[channel].ao_regs->selph2,
0x7 << SELPH2_TXDLY_DQSGATE_SHIFT |
0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT,
selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT |
selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT);
clrsetbits32(&ch[channel].ao_regs->selph2,
0x7 << SELPH2_TXDLY_DQSGATE_SHIFT |
0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT,
selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT |
selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT);
/* dly_DQSGATE and dly_DQSGATE_P1 */
clrsetbits_le32(&ch[channel].ao_regs->selph5,
0x3 << SELPH5_DLY_DQSGATE_SHIFT |
0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT,
(curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT |
(curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT);
clrsetbits32(&ch[channel].ao_regs->selph5,
0x3 << SELPH5_DLY_DQSGATE_SHIFT |
0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT,
(curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT |
(curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT);
}
static void set_gw_fine_factor(u32 channel, u8 curr_val, u8 rank)
{
u32 set = curr_val & (0x7f << DQSIEN_DQS0IEN_SHIFT);
clrsetbits_le32(&ch[channel].ao_regs->dqsien[rank],
0x7f << DQSIEN_DQS0IEN_SHIFT |
0x7f << DQSIEN_DQS1IEN_SHIFT |
0x7f << DQSIEN_DQS2IEN_SHIFT |
0x7f << DQSIEN_DQS3IEN_SHIFT,
set << DQSIEN_DQS0IEN_SHIFT |
set << DQSIEN_DQS1IEN_SHIFT |
set << DQSIEN_DQS2IEN_SHIFT |
set << DQSIEN_DQS3IEN_SHIFT);
clrsetbits32(&ch[channel].ao_regs->dqsien[rank],
0x7f << DQSIEN_DQS0IEN_SHIFT |
0x7f << DQSIEN_DQS1IEN_SHIFT |
0x7f << DQSIEN_DQS2IEN_SHIFT |
0x7f << DQSIEN_DQS3IEN_SHIFT,
set << DQSIEN_DQS0IEN_SHIFT |
set << DQSIEN_DQS1IEN_SHIFT |
set << DQSIEN_DQS2IEN_SHIFT |
set << DQSIEN_DQS3IEN_SHIFT);
}
static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl)
@@ -249,33 +249,33 @@ static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl)
curr_val_p1 = curr_val + 2; /* diff is 0.5T */
clrsetbits_le32(&ch[channel].ao_regs->dqsctl2,
0xf << DQSCTL2_DQSINCTL_SHIFT,
dqsinctl << DQSCTL2_DQSINCTL_SHIFT);
clrsetbits32(&ch[channel].ao_regs->dqsctl2,
0xf << DQSCTL2_DQSINCTL_SHIFT,
dqsinctl << DQSCTL2_DQSINCTL_SHIFT);
/* TXDLY_R1DQSGATE and TXDLY_R1DQSGATE_P1 */
r1dqsgate = (curr_val >> 2) - dqsinctl;
r1dqsgate_p1 = (curr_val_p1 >> 2) - dqsinctl;
clrsetbits_le32(&ch[channel].ao_regs->selph6_1,
0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT |
0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT,
r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT |
r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT);
clrsetbits32(&ch[channel].ao_regs->selph6_1,
0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT |
0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT,
r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT |
r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT);
/* dly_R1DQSGATE and dly_R1DQSGATE_P1 */
clrsetbits_le32(&ch[channel].ao_regs->selph6_1,
0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT |
0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT,
(curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT |
(curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT);
clrsetbits32(&ch[channel].ao_regs->selph6_1,
0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT |
0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT,
(curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT |
(curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT);
}
static void dqs_gw_counter_reset(u32 channel)
{
/* reset dqs counter (1 to 0) */
setbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);
clrbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);
setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);
clrbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);
dramc_phy_reset(channel);
}
@@ -357,15 +357,15 @@ void rx_dqs_gating_cal(u32 channel, u8 rank,
u8 gw_coarse_val, gw_fine_val;
/* disable HW gating */
clrbits_le32(&ch[channel].ao_regs->dqscal0,
clrbits32(&ch[channel].ao_regs->dqscal0,
1 << DQSCAL0_STBCALEN_SHIFT);
/* enable DQS gating window counter */
setbits_le32(&ch[channel].ao_regs->dqsctl1,
setbits32(&ch[channel].ao_regs->dqsctl1,
1 << DQSCTL1_DQSIENMODE_SHIFT);
setbits_le32(&ch[channel].ao_regs->spcmd,
setbits32(&ch[channel].ao_regs->spcmd,
1 << SPCMD_DQSGCNTEN_SHIFT);
/* dual-phase DQS clock gating control enabling */
setbits_le32(&ch[channel].ddrphy_regs->dqsgctl,
setbits32(&ch[channel].ddrphy_regs->dqsgctl,
1 << DQSGCTL_DQSGDUALP_SHIFT);
/* gating calibration value */
@@ -418,7 +418,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel,
dqsinctl = (dqsinctl >> DQSCTL1_DQSINCTL_SHIFT) & (0xf << 0);
/* swap cs0 and cs1 */
setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
/* rank 1 gw calibration */
rx_dqs_gating_cal(channel, 1, sdram_params);
@@ -429,7 +429,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel,
set_gw_fine_factor(channel, opt_gw_fine_value[channel][1], 1);
/* swap cs back */
clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
/* set rank 0 coarse tune and fine tune back */
set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][0]);
@@ -446,15 +446,15 @@ void dramc_rankinctl_config(u32 channel,
value = min(opt_gw_coarse_value[channel][0],
opt_gw_coarse_value[channel][1]) >> 2;
clrsetbits_le32(&ch[channel].ao_regs->dummy, 0xf, value);
clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value);
/* RANKINCTL = RANKINCTL_ROOT1 */
clrsetbits_le32(&ch[channel].ao_regs->dqscal1,
0xf << 16, value << 16);
clrsetbits32(&ch[channel].ao_regs->dqscal1,
0xf << 16, value << 16);
}
/* disable per-bank refresh when refresh rate >= 5 */
setbits_le32(&ch[channel].ao_regs->rkcfg,
1 << RKCFG_PBREF_DISBYRATE_SHIFT);
setbits32(&ch[channel].ao_regs->rkcfg,
1 << RKCFG_PBREF_DISBYRATE_SHIFT);
}
u32 dram_k_perbit(u32 channel)
@@ -624,11 +624,11 @@ void clk_duty_cal(u32 channel)
max_duty_sel = max_duty = 1;
clrsetbits_le32(&ch[channel].ddrphy_regs->phyclkduty,
0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT |
1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT,
1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT |
max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT);
clrsetbits32(&ch[channel].ddrphy_regs->phyclkduty,
0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT |
1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT,
1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT |
max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT);
max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty);
@@ -639,26 +639,26 @@ void clk_duty_cal(u32 channel)
static void set_dle_factor(u32 channel, u8 curr_val)
{
clrsetbits_le32(&ch[channel].ao_regs->ddr2ctl,
0x7 << DDR2CTL_DATLAT_SHIFT,
(curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT);
clrsetbits32(&ch[channel].ao_regs->ddr2ctl,
0x7 << DDR2CTL_DATLAT_SHIFT,
(curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT);
clrsetbits_le32(&ch[channel].ao_regs->padctl4,
0x1 << PADCTL4_DATLAT3_SHIFT,
((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT);
clrsetbits32(&ch[channel].ao_regs->padctl4,
0x1 << PADCTL4_DATLAT3_SHIFT,
((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT);
clrsetbits_le32(&ch[channel].ao_regs->phyctl1,
0x1 << PHYCTL1_DATLAT4_SHIFT,
((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT);
clrsetbits32(&ch[channel].ao_regs->phyctl1,
0x1 << PHYCTL1_DATLAT4_SHIFT,
((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT);
clrsetbits_le32(&ch[channel].ao_regs->misc,
0x1f << MISC_DATLAT_DSEL_SHIFT,
(curr_val - 8) << MISC_DATLAT_DSEL_SHIFT);
clrsetbits32(&ch[channel].ao_regs->misc,
0x1f << MISC_DATLAT_DSEL_SHIFT,
(curr_val - 8) << MISC_DATLAT_DSEL_SHIFT);
/* optimize bandwidth for HW run time test engine use */
clrsetbits_le32(&ch[channel].ao_regs->misc,
0x1f << MISC_LATNORMP_SHIFT,
(curr_val - 3) << MISC_LATNORMP_SHIFT);
clrsetbits32(&ch[channel].ao_regs->misc,
0x1f << MISC_LATNORMP_SHIFT,
(curr_val - 3) << MISC_LATNORMP_SHIFT);
}
void dual_rank_rx_datlat_cal(u32 channel,
@@ -670,7 +670,7 @@ void dual_rank_rx_datlat_cal(u32 channel,
r0_dle_setting = rx_datlat_cal(channel, 0, sdram_params);
/* swap cs0 and cs1 */
setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
/* set rank 1 coarse tune and fine tune back */
set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][1]);
@@ -684,7 +684,7 @@ void dual_rank_rx_datlat_cal(u32 channel,
set_gw_fine_factor(channel, opt_gw_fine_value[channel][0], 0);
/* swap cs back */
clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
/* output dle setting of rank 0 and 1 */
dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n"
@@ -715,7 +715,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank,
channel, rank);
dramc_dbg_msg("=========================================\n");
clrbits_le32(&ch[channel].ao_regs->mckdly,
clrbits32(&ch[channel].ao_regs->mckdly,
0x11 << MCKDLY_DQIENQKEND_SHIFT |
0x1 << MCKDLY_DQIENLAT_SHIFT);

40
src/soc/mediatek/mt8173/dsi.c
View File

@@ -40,16 +40,16 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
write32(&mipi_tx0->dsi_bg_con, reg);
udelay(30);
clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
setbits_le32(&mipi_tx0->dsi_con,
RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
setbits32(&mipi_tx0->dsi_con,
RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
RG_DSI_MPPLL_SDM_PWR_ON);
clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
RG_DSI_MPPLL_SDM_PWR_ON);
clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
if (data_rate > 500) {
txdiv0 = 0;
@@ -70,9 +70,9 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
txdiv1 = 2;
}
clrsetbits_le32(&mipi_tx0->dsi_pll_con0,
RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
clrsetbits32(&mipi_tx0->dsi_pll_con0,
RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
/**
* PLL PCW config
@@ -86,25 +86,25 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
pcw /= 13;
write32(&mipi_tx0->dsi_pll_con2, pcw);
setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
for (i = 0; i < lanes; i++)
setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
udelay(40);
clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
}
void mtk_dsi_reset(void)
{
setbits_le32(&dsi0->dsi_con_ctrl, 3);
clrbits_le32(&dsi0->dsi_con_ctrl, 1);
setbits32(&dsi0->dsi_con_ctrl, 3);
clrbits32(&dsi0->dsi_con_ctrl, 1);
}
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
@@ -131,7 +131,7 @@ void mtk_dsi_pin_drv_ctrl(void)
struct stopwatch sw;
uint32_t pwr_ack;
setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
stopwatch_init_usecs_expire(&sw, 1000);
@@ -143,5 +143,5 @@ void mtk_dsi_pin_drv_ctrl(void)
pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
} while (pwr_ack == 0);
clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
}

8
src/soc/mediatek/mt8173/emi.c
View File

@@ -166,11 +166,11 @@ size_t sdram_size(void)
static void init_4GB_mode(void)
{
if (sdram_size() == (size_t)4 * GiB) {
setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
setbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
setbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
} else {
clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
clrbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
clrbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
}
}

4
src/soc/mediatek/mt8173/gpio_init.c
View File

@@ -25,14 +25,14 @@
*/
static void set_gpi_from_mipi(void)
{
setbits_le32(&mt8173_mipi->mipi_rx_ana4c,
setbits32(&mt8173_mipi->mipi_rx_ana4c,
1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */
1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */
1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */
1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */
1 << 24); /* RF_MIPI_GPI4_IES GPI51 */
setbits_le32(&mt8173_mipi->mipi_rx_ana50,
setbits32(&mt8173_mipi->mipi_rx_ana50,
1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */
1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */
1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */

54
src/soc/mediatek/mt8173/pll.c
View File

@@ -296,7 +296,7 @@ static const struct rate rates[] = {
void pll_set_pcw_change(const struct pll *pll)
{
setbits_le32(pll->pcw_reg, PLL_PCW_CHG);
setbits32(pll->pcw_reg, PLL_PCW_CHG);
}
void mt_pll_init(void)
@@ -313,7 +313,7 @@ void mt_pll_init(void)
* xPLL PWR ON
**************/
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
setbits32(plls[i].pwr_reg, PLL_PWR_ON);
/* wait for xPLL_PWR_ON ready (min delay is 1us) */
udelay(PLL_PWR_ON_DELAY);
@@ -322,7 +322,7 @@ void mt_pll_init(void)
* xPLL ISO Disable
*******************/
for (i = 0; i < APMIXED_NR_PLL; i++)
clrbits_le32(plls[i].pwr_reg, PLL_ISO);
clrbits32(plls[i].pwr_reg, PLL_ISO);
/********************
* xPLL Frequency Set
@@ -334,7 +334,7 @@ void mt_pll_init(void)
* xPLL Frequency Enable
************************/
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].reg, PLL_EN);
setbits32(plls[i].reg, PLL_EN);
udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */
@@ -343,7 +343,7 @@ void mt_pll_init(void)
****************/
for (i = 0; i < APMIXED_NR_PLL; i++) {
if (plls[i].rstb_shift != NO_RSTB_SHIFT)
setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
}
/**************
@@ -351,7 +351,7 @@ void mt_pll_init(void)
***************/
/* enable infrasys DCM */
setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1);
setbits32(&mt8173_infracfg->top_dcmctl, 0x1);
write32(&mtk_topckgen->clk_mode, 0x1);
write32(&mtk_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */
@@ -374,16 +374,16 @@ void mt_pll_init(void)
void mt_pll_enable_ssusb_clk(void)
{
/* set RG_LTECLKSQ_EN */
setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1);
setbits32(&mtk_apmixed->ap_pll_con0, 0x1);
udelay(100); /* wait for PLL stable */
/* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */
setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1 << 1);
setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1);
setbits32(&mtk_apmixed->ap_pll_con0, 0x1 << 1);
setbits32(&mtk_apmixed->ap_pll_con2, 0x1);
udelay(100); /* wait for PLL stable */
/* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */
setbits_le32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));
setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1));
}
@@ -391,7 +391,7 @@ void mt_pll_enable_ssusb_clk(void)
void mt_pll_post_init(void)
{
/* CPU clock divide by 1 */
clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff);
clrbits32(&mt8173_infracfg->top_ckdiv1, 0x3ff);
/* select ARMPLL */
write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1);
@@ -414,20 +414,20 @@ void mt_pll_set_aud_div(u32 rate)
if (apll1) {
/* mclk */
clrbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mtk_topckgen->clk_auddiv_1, 0xff << 8,
mclk_div << 8);
clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8,
mclk_div << 8);
/* bclk */
clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 24,
7 << 24);
clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24,
7 << 24);
} else {
/* mclk */
setbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mtk_topckgen->clk_auddiv_2, 0xff << 8,
mclk_div << 8);
setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8,
mclk_div << 8);
/* bclk */
clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 28,
7 << 28);
clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28,
7 << 28);
}
}
@@ -441,19 +441,19 @@ void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
u32 mpll_sdm_pcw_20_0 = 0xF13B1;
/* disable MPLL for adjusting memory clk frequency */
clrbits_le32(&mtk_apmixed->mpll_con0, BIT(0));
clrbits32(&mtk_apmixed->mpll_con0, BIT(0));
/* MPLL configuration: mode selection */
setbits_le32(&mtk_apmixed->mpll_con0, BIT(16));
clrbits_le32(&mtk_apmixed->mpll_con0, 0x7 << 4);
clrbits_le32(&mtk_apmixed->pll_test_con0, 1 << 31);
setbits32(&mtk_apmixed->mpll_con0, BIT(16));
clrbits32(&mtk_apmixed->mpll_con0, 0x7 << 4);
clrbits32(&mtk_apmixed->pll_test_con0, 1 << 31);
/* set RG_MPLL_SDM_PCW for feedback divide ratio */
clrsetbits_le32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);
clrsetbits32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);
}
void mt_mem_pll_config_post(void)
{
/* power up sequence starts: enable MPLL */
setbits_le32(&mtk_apmixed->mpll_con0, BIT(0));
setbits32(&mtk_apmixed->mpll_con0, BIT(0));
}
void mt_mem_pll_mux(void)

4
src/soc/mediatek/mt8173/pmic_wrap.c
View File

@@ -170,11 +170,11 @@ s32 pwrap_init(void)
s32 sub_return1 = 0;
u16 rdata = 0x0;
setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
setbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
/* add 1us delay for toggling SW reset */
udelay(1);
/* clear reset bit */
clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
clrbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST);
/* Enable DCM */
write32(&mtk_pwrap->dcm_en, 3);

8
src/soc/mediatek/mt8173/spi.c
View File

@@ -47,10 +47,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
SPI_CFG1_TICK_DLY_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
SPI_CFG1_TICK_DLY_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}
static const struct spi_ctrlr spi_flash_ctrlr = {

8
src/soc/mediatek/mt8183/auxadc.c
View File

@@ -51,19 +51,19 @@ static void mt_auxadc_update_cali(void)
}
static uint32_t auxadc_get_rawdata(int channel)
{
setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1)));
clrbits_le32(&mtk_auxadc->con1, 1 << channel);
clrbits32(&mtk_auxadc->con1, 1 << channel);
assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12))));
setbits_le32(&mtk_auxadc->con1, 1 << channel);
setbits32(&mtk_auxadc->con1, 1 << channel);
udelay(25);
assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12)));
uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
return value;
}

8
src/soc/mediatek/mt8183/ddp.c
View File

@@ -42,7 +42,7 @@ static void disp_config_main_path_mutex(void)
static void ovl_bgclr_in_sel(u32 idx)
{
setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
}
static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
@@ -74,10 +74,10 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
static void disp_clock_on(void)
{
clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
CG_CON1_DISP_DSI0_INTERFACE);
clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
CG_CON1_DISP_DSI0_INTERFACE);
}
void mtk_ddp_init(void)

966
src/soc/mediatek/mt8183/dramc_init_setting.c
View File

File diff suppressed because it is too large Load Diff

214
src/soc/mediatek/mt8183/dramc_pi_basic_api.c
View File

@@ -48,7 +48,7 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage)
}
}
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8);
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8);
}
void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
@@ -60,29 +60,29 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
broadcast_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
write32(&ch[0].phy.misc_spm_ctrl2, 0x0);
write32(&ch[0].phy.misc_spm_ctrl0, 0x0);
clrbits_le32(&ch[0].ao.impcal, 0x1 << 31);
clrbits32(&ch[0].ao.impcal, 0x1 << 31);
impcal_bak = read32(&ch[0].ao.impcal);
dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP);
clrbits_le32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6);
clrsetbits_le32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24);
clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4);
clrbits32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6);
clrsetbits32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24);
clrsetbits32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4);
udelay(1);
dramc_dbg("impedance: K DRVP\n");
setbits_le32(&ch[0].ao.impcal, 0x1 << 23);
setbits_le32(&ch[0].ao.impcal, 0x1 << 22);
clrbits_le32(&ch[0].ao.impcal, 0x1 << 21);
clrbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
setbits32(&ch[0].ao.impcal, 0x1 << 23);
setbits32(&ch[0].ao.impcal, 0x1 << 22);
clrbits32(&ch[0].ao.impcal, 0x1 << 21);
clrbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11);
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) {
impx_drv = (impx_drv == 16) ? 29 : impx_drv;
clrsetbits_le32(&ch[0].ao.shu[0].impcal1,
clrsetbits32(&ch[0].ao.shu[0].impcal1,
0x1f << 4, impx_drv << 4);
udelay(1);
imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
@@ -100,17 +100,17 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
dramc_dbg("impedance: K ODTN\n");
dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN);
clrbits_le32(&ch[0].ao.impcal, 0x1 << 22);
clrbits32(&ch[0].ao.impcal, 0x1 << 22);
if (term == ODT_ON)
setbits_le32(&ch[0].ao.impcal, 0x1 << 21);
clrsetbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11,
setbits32(&ch[0].ao.impcal, 0x1 << 21);
clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11,
DRVP_result << 4 | 0x1f << 11);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) {
impx_drv = (impx_drv == 16) ? 29 : impx_drv;
clrsetbits_le32(&ch[0].ao.shu[0].impcal1,
clrsetbits32(&ch[0].ao.shu[0].impcal1,
0x1f << 11, impx_drv << 11);
udelay(1);
imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
@@ -163,31 +163,31 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2];
sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP);
/* DQ */
clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
(sw_impedance[dq_term][0] << 5) |
(sw_impedance[dq_term][1] << 0));
clrsetbits_le32(&ch[0].ao.shu[0].drving[1],
clrsetbits32(&ch[0].ao.shu[0].drving[1],
(0x1f << 25) | (0x1f << 20) | (1 << 31),
(sw_impedance[dq_term][0] << 25) |
(sw_impedance[dq_term][1] << 20) | (!dq_term << 31));
clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0),
clrsetbits32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0),
(sw_impedance[dq_term][2] << 5) |
(sw_impedance[dq_term][3] << 0));
clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20),
clrsetbits32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20),
(sw_impedance[dq_term][2] << 25) |
(sw_impedance[dq_term][3] << 20));
/* DQS */
for (u8 i = 0; i <= 2; i += 2) {
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
clrsetbits32(&ch[0].ao.shu[0].drving[i],
(0x1f << 25) | (0x1f << 20),
(sw_impedance[dq_term][i] << 25) |
(sw_impedance[dq_term][i + 1] << 20));
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
clrsetbits32(&ch[0].ao.shu[0].drving[i],
(0x1f << 15) | (0x1f << 10),
(sw_impedance[dq_term][i] << 15) |
(sw_impedance[dq_term][i + 1] << 10));
@@ -195,19 +195,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
/* CMD & CLK */
for (u8 i = 1; i <= 3; i += 2) {
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
clrsetbits32(&ch[0].ao.shu[0].drving[i],
(0x1f << 15) | (0x1f << 10),
(sw_impedance[ca_term][i - 1] << 15) |
(sw_impedance[ca_term][i] << 10));
clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
clrsetbits32(&ch[0].ao.shu[0].drving[i],
(0x1f << 5) | (0x1f << 0),
(sw_impedance[ca_term][i - 1] << 5) |
(sw_impedance[ca_term][i] << 0));
}
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17,
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17,
sw_impedance[ca_term][0] << 17);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
sw_impedance[ca_term][1] << 22);
SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3],
@@ -215,34 +215,34 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0],
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
}
static void transfer_pll_to_spm_control(void)
{
u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3;
clrsetbits_le32(&mtk_spm->poweron_config_set,
clrsetbits32(&mtk_spm->poweron_config_set,
(0xffff << 16) | (0x1 << 0),
(0xb16 << 16) | (0x1 << 0));
/* Set SPM pinmux */
clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12));
setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0);
setbits32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12));
setbits32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0);
shu_lev = (shu_lev == 1) ? 2 : 1;
clrsetbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28);
clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2,
clrsetbits32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28);
clrsetbits32(&mtk_spm->dramc_dpy_clk_sw_con2,
0x3 << 2, shu_lev << 2);
udelay(1);
for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {
clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31);
clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31);
clrbits32(&ch[chn].phy.pll1, 0x1 << 31);
clrbits32(&ch[chn].phy.pll2, 0x1 << 31);
}
}
@@ -254,50 +254,50 @@ static void dramc_rx_input_delay_tracking(u8 chn)
/* DVS mode to RG mode */
for (size_t r = 0; r < 2; r++)
for (size_t b = 0; b < 2; b++)
clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30);
clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30);
clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9);
clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9);
clrsetbits32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9);
clrsetbits32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9);
for (size_t r = 0; r < 2; r++)
for (size_t b = 0; b < 2; b++) {
clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29);
clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7],
clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29);
clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[7],
(0x3f << 0) | (0x3f << 8) |
(0x7f << 16) | (0x7f << 24),
(0x0 << 0) | (0x3f << 8) |
(0x0 << 16) | (0x7f << 24));
clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[1],
clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[1],
(0xffff << 16) | (0xffff << 0),
(0x2 << 16) | (0x2 << 0));
/* DQ/DQS Rx DLY adjustment for tracking mode */
clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2],
clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2],
(0x3 << 26) | (0x3 << 24) |
(0x3 << 18) | (0x3 << 16));
}
/* Rx DLY tracking setting (Static) */
clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0],
clrsetbits32(&ch[chn].phy.b0_rxdvs[0],
(0x1 << 29) | (0xf << 4) | (0x1 << 0),
(0x1 << 29) | (0x0 << 4) | (0x1 << 0));
clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0],
clrsetbits32(&ch[chn].phy.b1_rxdvs[0],
(0x1 << 29) | (0xf << 4) | (0x1 << 0),
(0x1 << 29) | (0x0 << 4) | (0x1 << 0));
for (u8 b = 0; b < 2; b++) {
clrsetbits_le32(&ch[chn].phy.b[b].dq[9],
clrsetbits32(&ch[chn].phy.b[b].dq[9],
(0x7 << 28) | (0x7 << 24),
(0x1 << 28) | (0x0 << 24));
setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31);
setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31);
}
clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31));
setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31));
setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31));
setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31));
for (u8 rank = RANK_0; rank < RANK_MAX; rank++)
for (u8 b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
(0x3 << 30) | (0x1 << 28) | (0x1 << 23),
(0x2 << 30) | (0x1 << 28) | (0x1 << 23));
@@ -305,29 +305,29 @@ static void dramc_rx_input_delay_tracking(u8 chn)
static void dramc_hw_dqs_gating_tracking(u8 chn)
{
clrsetbits_le32(&ch[chn].ao.stbcal,
clrsetbits32(&ch[chn].ao.stbcal,
(0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4),
(0x3 << 26) | (0x1 << 0));
clrsetbits_le32(&ch[chn].ao.stbcal1,
clrsetbits32(&ch[chn].ao.stbcal1,
(0xffff << 16) | (0x1 << 8) | (0x1 << 6),
(0x1 << 16) | (0x1 << 8) | (0x1 << 6));
clrsetbits_le32(&ch[chn].phy.misc_ctrl0,
clrsetbits32(&ch[chn].phy.misc_ctrl0,
(0x1 << 24) | (0x1f << 11) | (0xf << 0),
(0x1 << 24) | (0x0 << 11) | (0x0 << 0));
clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 31);
clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 31);
clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 31);
clrbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 31);
clrbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 31);
clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31);
}
static void dramc_hw_gating_init(void)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
clrbits_le32(&ch[chn].ao.stbcal,
clrbits32(&ch[chn].ao.stbcal,
(0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));
setbits_le32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28));
setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 24);
setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28));
setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24);
dramc_hw_dqs_gating_tracking(chn);
}
@@ -335,28 +335,28 @@ static void dramc_hw_gating_init(void)
static void dramc_impedance_tracking_enable(void)
{
setbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 10);
setbits32(&ch[0].phy.misc_ctrl0, 0x1 << 10);
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) |
setbits32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) |
(0x1 << 26) | (0x1 << 17) | (0x7 << 11));
clrbits_le32(&ch[chn].ao.impcal, 0x1 << 30);
setbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 18);
setbits_le32(&ch[chn].ao.impcal, 0x1 << 19);
clrbits32(&ch[chn].ao.impcal, 0x1 << 30);
setbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 18);
setbits32(&ch[chn].ao.impcal, 0x1 << 19);
}
setbits_le32(&ch[0].ao.impcal, 0x1 << 14);
setbits32(&ch[0].ao.impcal, 0x1 << 14);
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3));
setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3));
}
static void dramc_phy_low_power_enable(void)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
for (size_t b = 0; b < 2; b++) {
clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2],
clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2],
0x3fffff << 10);
write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800);
}
clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],
clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2],
0x3fffff << 10, 0x2 << 10);
}
write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000);
@@ -365,67 +365,67 @@ static void dramc_phy_low_power_enable(void)
static void dramc_dummy_read_for_tracking_enable(u8 chn)
{
setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16);
setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16);
for (size_t r = 0; r < 2; r++)
for (size_t i = 0; i < 4; i++)
write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i],
0xaaaa5555);
clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
for (size_t r = 0; r < 2; r++) {
clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr,
clrsetbits32(&ch[chn].ao.rk[r].dummy_rd_adr,
(0x1ffff << 0) | (0x7ff << 17) | (0xf << 28),
(0xffff << 0) | (0x3f0 << 17));
clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0);
clrbits32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0);
}
clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
clrbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
}
static void dramc_set_CKE_2_rank_independent(u8 chn)
{
clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2);
clrsetbits_le32(&ch[chn].ao.ckectrl,
clrsetbits32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2);
clrsetbits32(&ch[chn].ao.ckectrl,
(0x1 << 1) | (0xf << 8) | (0x7 << 13),
(0x4 << 8) | (0x2 << 13));
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
setbits_le32(&ch[chn].ao.shu[shu].conf[2],
setbits32(&ch[chn].ao.shu[shu].conf[2],
(0x1 << 29) | (0x1 << 31));
clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9);
clrbits32(&ch[chn].ao.dramctrl, 0x1 << 9);
}
static void dramc_pa_improve(u8 chn)
{
clrbits_le32(&ch[chn].ao.clkar, 0xffff);
clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12);
clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
clrbits32(&ch[chn].ao.clkar, 0xffff);
clrbits32(&ch[chn].ao.srefctrl, 0xf << 12);
clrbits32(&ch[chn].ao.zqcs, 0x1 << 19);
clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
clrbits32(&ch[chn].ao.zqcs, 0x1 << 19);
clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2);
clrbits32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2);
}
static void dramc_enable_dramc_dcm(void)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,
clrsetbits32(&ch[chn].ao.dramc_pd_ctrl,
(0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),
(0x7 << 0) | (0x1 << 30) | (0x1 << 31));
setbits_le32(&ch[chn].ao.clkar, 0x1 << 31);
setbits32(&ch[chn].ao.clkar, 0x1 << 31);
}
}
void dramc_runtime_config(void)
{
clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29);
clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29);
clrbits32(&ch[0].ao.refctrl0, 0x1 << 29);
clrbits32(&ch[1].ao.refctrl0, 0x1 << 29);
transfer_pll_to_spm_control();
setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
/* RX_TRACKING: ON */
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
@@ -438,7 +438,7 @@ void dramc_runtime_config(void)
/* HW_GATING DBG: OFF */
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
clrbits_le32(&ch[chn].ao.stbcal2,
clrbits32(&ch[chn].ao.stbcal2,
(0x3 << 4) | (0x3 << 8) | (0x1 << 28));
/* DUMMY_READ_FOR_TRACKING: ON */
@@ -446,8 +446,8 @@ void dramc_runtime_config(void)
dramc_dummy_read_for_tracking_enable(chn);
/* ZQCS_ENABLE_LP4: ON */
clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);
clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30);
clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30);
clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30);
/* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */
dramc_phy_low_power_enable();
@@ -456,7 +456,7 @@ void dramc_runtime_config(void)
/* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry,
clrbits32(&ch[chn].ao.shu[shu].dqsg_retry,
(0x1 << 1) | (0x3 << 13));
/* SPM_CONTROL_AFTERK: ON */
@@ -470,33 +470,33 @@ void dramc_runtime_config(void)
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
/* TEMP_SENSOR: ON */
clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28);
setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11));
clrbits32(&ch[chn].ao.spcmdctrl, 0x3 << 28);
setbits32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11));
/* PER_BANK_REFRESH: ON */
clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18);
/* HW_SAVE_FOR_SR: ON */
clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28));
setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0);
clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22);
clrbits32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28));
setbits32(&ch[chn].ao.refctrl1, 0x1 << 0);
clrsetbits32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22);
/* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */
dramc_set_CKE_2_rank_independent(chn);
/* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */
clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2));
clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19);
clrbits32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2));
clrbits32(&ch[chn].ao.clkar, 0x1 << 19);
/* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */
dramc_pa_improve(chn);
/* DRAM DRS DISABLE */
clrsetbits_le32(&ch[chn].ao.drsctrl,
clrsetbits32(&ch[chn].ao.drsctrl,
(0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6),
(0x1 << 19) | (0x3 << 12) | (0x8 << 8) |
(0x3 << 4) | (0x1 << 2) | (0x1 << 0));
setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26);
setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
}
enable_emi_dcm();

238
src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
View File

@@ -154,8 +154,8 @@ static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_t
tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT);
}
clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift);
clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift);
clrsetbits32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift);
clrsetbits32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift);
}
static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune)
@@ -279,36 +279,36 @@ static void dramc_write_dbi_onoff(bool onoff)
static void dramc_phy_dcm_2_channel(u8 chn, bool en)
{
clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8),
clrsetbits32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8),
((en ? 0 : 0x1) << 19) | ((en ? 0 : 0x1ff) << 9) | (1 << 8));
for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&shu->b[b].dq[8], 0x1fff << 19,
clrsetbits32(&shu->b[b].dq[8], 0x1fff << 19,
((en ? 0 : 0x7ff) << 22) | (0x1 << 21) |
((en ? 0 : 0x3) << 19));
clrbits_le32(&shu->ca_cmd[8], 0x1fff << 19);
clrbits32(&shu->ca_cmd[8], 0x1fff << 19);
}
clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20),
clrsetbits32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20),
((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20));
}
void dramc_enable_phy_dcm(bool en)
{
for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) {
clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20);
clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20);
clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20);
clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20);
clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20);
clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20);
for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
setbits_le32(&shu->b[0].dll[0], 0x1);
setbits_le32(&shu->b[1].dll[0], 0x1);
setbits_le32(&shu->ca_dll[0], 0x1);
setbits32(&shu->b[0].dll[0], 0x1);
setbits32(&shu->b[1].dll[0], 0x1);
setbits32(&shu->ca_dll[0], 0x1);
}
clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,
clrsetbits32(&ch[chn].ao.dramc_pd_ctrl,
(0x1 << 0) | (0x1 << 1) | (0x1 << 2) |
(0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),
((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) |
@@ -324,16 +324,16 @@ void dramc_enable_phy_dcm(bool en)
write32(&ch[chn].phy.misc_cg_ctrl2,
0x8060033e | (0x40 << (en ? 0x1 : 0)));
clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26,
clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26,
(en ? 0 : 0x3) << 26);
for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
u32 mask = 0x7 << 17;
u32 value = (en ? 0x7 : 0) << 17;
struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
clrsetbits_le32(&shu->b[0].dq[7], mask, value);
clrsetbits_le32(&shu->b[1].dq[7], mask, value);
clrsetbits_le32(&shu->ca_cmd[7], mask, value);
clrsetbits32(&shu->b[0].dq[7], mask, value);
clrsetbits32(&shu->b[1].dq[7], mask, value);
clrsetbits32(&shu->ca_cmd[7], mask, value);
}
dramc_phy_dcm_2_channel(chn, en);
@@ -346,31 +346,31 @@ static void dramc_reset_delay_chain_before_calibration(void)
for (size_t rank = 0; rank < RANK_MAX; rank++) {
struct dramc_ddrphy_regs_shu_rk *rk;
rk = &ch[chn].phy.shu[0].rk[rank];
clrbits_le32(&rk->ca_cmd[0], 0xffffff << 0);
clrbits_le32(&rk->b[0].dq[0], 0xfffffff << 0);
clrbits_le32(&rk->b[1].dq[0], 0xfffffff << 0);
clrbits_le32(&rk->b[0].dq[1], 0xf << 0);
clrbits_le32(&rk->b[1].dq[1], 0xf << 0);
clrbits32(&rk->ca_cmd[0], 0xffffff << 0);
clrbits32(&rk->b[0].dq[0], 0xfffffff << 0);
clrbits32(&rk->b[1].dq[0], 0xfffffff << 0);
clrbits32(&rk->b[0].dq[1], 0xf << 0);
clrbits32(&rk->b[1].dq[1], 0xf << 0);
}
}
void dramc_hw_gating_onoff(u8 chn, bool on)
{
clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14,
clrsetbits32(&ch[chn].ao.shuctrl2, 0x3 << 14,
(on ? 0x3 : 0) << 14);
clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28);
clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24);
clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22);
clrsetbits32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28);
clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24);
clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22);
}
static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn)
{
struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0];
clrsetbits_le32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20);
clrsetbits_le32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20);
clrbits_le32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13));
clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13));
clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20);
clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20);
clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13));
clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13));
}
void dramc_apply_config_before_calibration(u8 freq_group)
@@ -378,55 +378,55 @@ void dramc_apply_config_before_calibration(u8 freq_group)
dramc_enable_phy_dcm(false);
dramc_reset_delay_chain_before_calibration();
setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16);
setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24);
clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);
setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16);
setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24);
clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);
for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);
setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);
clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18);
clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31);
clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);
clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26);
clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25);
clrbits32(&ch[0].ao.dramctrl, 0x1 << 18);
clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31);
clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30);
clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26);
clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25);
dramc_write_dbi_onoff(false);
dramc_read_dbi_onoff(false);
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29);
setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24);
setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29);
setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24);
for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
setbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));
clrbits32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));
dramc_hw_gating_onoff(chn, false);
clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28);
clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28);
setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24);
setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17);
clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);
clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18);
clrbits32(&ch[chn].ao.mrs, 0x3 << 24);
setbits32(&ch[chn].ao.mpc_option, 0x1 << 17);
clrsetbits32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);
clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
dramc_rx_input_delay_tracking_init_by_freq(chn);
setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25);
setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0);
setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25);
setbits32(&ch[chn].ao.drsctrl, 0x1 << 0);
if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600)
clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
else
setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
}
for (size_t r = 0; r < 2; r++) {
for (size_t b = 0; b < 2; b++)
clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],
clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
(0x1 << 28) | (0x1 << 23) | (0x3 << 30));
clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);
clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);
}
}
@@ -437,51 +437,51 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr)
mr->MR13Value & ~(0x1 << 3));
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
clrbits32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
}
void dramc_apply_config_after_calibration(const struct mr_value *mr)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000);
clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7);
clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2);
clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
clrbits32(&ch[chn].ao.refctrl1, 0x1 << 7);
clrbits32(&ch[chn].ao.shuctrl, 0x1 << 2);
clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
dramc_set_mr13_vrcg_to_Normal(chn, mr);
clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3);
clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3);
clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x3);
setbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 5);
setbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 5);
setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5);
clrbits32(&ch[chn].phy.b[0].dq[6], 0x3);
clrbits32(&ch[chn].phy.b[1].dq[6], 0x3);
clrbits32(&ch[chn].phy.ca_cmd[6], 0x3);
setbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 5);
setbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 5);
setbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 5);
clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24);
clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4);
clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf);
clrbits32(&ch[chn].ao.impcal, 0x3 << 24);
clrbits32(&ch[chn].phy.misc_imp_ctrl0, 0x4);
clrbits32(&ch[chn].phy.misc_cg_ctrl0, 0xf);
clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31);
clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25);
clrbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 31);
clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 25);
setbits_le32(&ch[chn].ao.spcmdctrl, 1 << 29);
setbits_le32(&ch[chn].ao.dqsoscr, 1 << 24);
setbits32(&ch[chn].ao.spcmdctrl, 1 << 29);
setbits32(&ch[chn].ao.dqsoscr, 1 << 24);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
clrbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
clrbits_le32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7));
clrbits32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7));
dramc_cke_fix_onoff(chn, false, false);
clrbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
clrbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
clrbits_le32(&ch[chn].ao.eyescan, 0x7 << 8);
clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
clrbits32(&ch[chn].ao.eyescan, 0x7 << 8);
clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
}
}
static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag)
{
for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 1 << 5,
clrsetbits32(&ch[chn].phy.b[b].dq[6], 1 << 5,
(flag ? 1 : 0) << 5);
}
@@ -600,7 +600,7 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr)
static void dramc_engine2_end(u8 chn, u32 dummy_rd)
{
clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17);
clrbits32(&ch[chn].ao.test2_4, 0x1 << 17);
write32(&ch[chn].ao.dummy_rd, dummy_rd);
}
@@ -717,12 +717,12 @@ static void dram_phy_reset(u8 chn)
{
SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1);
SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
clrbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
clrbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
udelay(1);
setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
setbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
setbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0);
}
@@ -737,18 +737,18 @@ static void dramc_set_gating_mode(u8 chn, bool mode)
}
for (size_t b = 0; b < 2; b++) {
clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14);
setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5);
clrsetbits32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14);
setbits32(&ch[chn].phy.b[b].dq[9], 0x1 << 5);
}
clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5);
setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30);
clrsetbits32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5);
setbits32(&ch[chn].ao.stbcal, 0x1 << 30);
clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
clrbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
clrbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
udelay(1);
setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
setbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
setbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
}
static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank)
@@ -773,7 +773,7 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank)
static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1)
{
clrsetbits_le32(addr, 0x77777777,
clrsetbits32(addr, 0x77777777,
(dly << 0) | (dly << 8) | (dly << 16) | (dly << 24) |
(dly_p1 << 4) | (dly_p1 << 12) | (dly_p1 << 20) | (dly_p1 << 28));
}
@@ -788,11 +788,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank,
dramc_rx_dqs_isi_pulse_cg_switch(chn, true);
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
0x77777777,
(best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) |
(best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,
0x77777777,
(best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) |
(best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12));
@@ -827,11 +827,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank,
}
}
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,
0x77777777,
(best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) |
(best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,
0x77777777,
(best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) |
(best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12));
@@ -1063,7 +1063,7 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank)
u16 temp_value = 0;
for (size_t b = 0; b < 2; b++)
clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
clrbits32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
@@ -1213,17 +1213,17 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk,
if (*dq_small_reg != dly_tune.coarse_tune_small) {
if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) {
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0],
clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0],
0x77777777, dly_large | (dly_large_oen << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2],
clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2],
0x77777777, dly_small | (dly_small_oen << 16));
}
if (type == TX_WIN_DQ_DQM) {
/* Large coarse_tune setting */
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1],
clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1],
0x77777777, dly_large | (dly_large_oen << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3],
clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3],
0x77777777, dly_small | (dly_small_oen << 16));
}
}
@@ -1480,13 +1480,13 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type,
}
for (size_t rank = rank_start; rank < RANK_MAX; rank++) {
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],
0x77777777, dq_large | (dq_large_oen << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],
0x77777777, dq_small | (dq_small_oen << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1],
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1],
0x77777777, dqm_large | (dqm_large_oen << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],
0x77777777, dqm_small | (dqm_small_oen << 16));
for (size_t byte = 0; byte < 2; byte++)
@@ -1503,15 +1503,15 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type,
if (type != TX_WIN_DQ_ONLY)
continue;
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f,
(dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) |
(dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16),
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16),
(dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16),
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16),
(dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16));
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16),
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16),
(dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16));
}
}
@@ -1525,7 +1525,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank,
for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) |
(dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0);
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value);
clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value);
}
dram_phy_reset(chn);
@@ -1538,7 +1538,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank,
(dly[index + 1].best_dqdly << 16) |
(dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0);
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num],
clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num],
0x3f3f3f3f, value);
}
}
@@ -1817,11 +1817,11 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group,
if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) {
for (size_t byte = 0; byte < 2; byte++) {
write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0);
clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1],
clrbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1],
0xf);
}
setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7);
setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7);
setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7);
setbits32(&ch[chn].ao.dqsoscr, 0x1 << 7);
if (fsp == FSP_1)
vref_step = 2;
}
@@ -2070,7 +2070,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
dqs, best_coarse_tune2t_p1[rank][dqs]);
}
clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
0x77777777,
(best_coarse_tune2t[rank][0] << 0) |
(best_coarse_tune2t[rank][1] << 8) |
@@ -2085,13 +2085,13 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,
clrsetbits32(&ch[chn].ao.shu[0].rankctl,
(0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf,
(read_dqsinctl << 28) | (rankinctl_root << 20) |
(rankinctl_root << 24) | rankinctl_root);
u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1;
clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1),
clrsetbits32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1),
(0xff << 8) | (0x9 << 2) | ROEN);
}

22
src/soc/mediatek/mt8183/dsi.c
View File

@@ -49,19 +49,19 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
txdiv1 = 0;
}
clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
udelay(30);
clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
pcw <<= 24;
pcw /= CLK26M_HZ / MHz;
write32(&mipi_tx->pll_con0, pcw);
clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
udelay(30);
setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
/* BG_LPF_EN / BG_CORE_EN */
write32(&mipi_tx->lane_con, 0x3fff0180);
@@ -69,13 +69,13 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
write32(&mipi_tx->lane_con, 0x3fff00c0);
/* Switch OFF each Lane */
clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
}
void mtk_dsi_reset(void)

38
src/soc/mediatek/mt8183/emi.c
View File

@@ -157,7 +157,7 @@ size_t sdram_size(void)
static void set_rank_info_to_conf(const struct sdram_params *params)
{
bool is_dual_rank = (params->emi_cona_val & (0x1 << 17)) != 0;
clrsetbits_le32(&ch[0].ao.rstmask, 0x1 << 12,
clrsetbits32(&ch[0].ao.rstmask, 0x1 << 12,
(is_dual_rank ? 0 : 1) << 12);
}
@@ -297,8 +297,8 @@ static void emi_init2(const struct sdram_params *params)
{
emi_esl_setting2();
setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
write32(&emi_regs->bwct0, 0x0a000705);
write32(&emi_regs->bwct0_3rd, 0x0);
@@ -311,14 +311,14 @@ static void emi_init2(const struct sdram_params *params)
static void dramc_init_pre_settings(void)
{
clrsetbits_le32(&ch[0].phy.ca_cmd[8],
clrsetbits32(&ch[0].phy.ca_cmd[8],
(0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) |
(0x1f << 8) | (0x1f << 0),
(0x1 << 19) | (0xa << 8) | (0xa << 0));
setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 12);
clrbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 13);
setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31);
setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 12);
clrbits32(&ch[0].phy.misc_ctrl1, 0x1 << 13);
setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31);
}
static void dramc_ac_timing_optimize(u8 freq_group)
@@ -331,20 +331,20 @@ static void dramc_ac_timing_optimize(u8 freq_group)
};
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],
clrsetbits32(&ch[chn].ao.shu[0].actim[3],
0xff << 16, rf_cab_opt[freq_group].rfc << 16);
clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t,
clrbits32(&ch[chn].ao.shu[0].ac_time_05t,
rf_cab_opt[freq_group].rfc_05t << 2);
clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],
clrsetbits32(&ch[chn].ao.shu[0].actim[4],
0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0);
}
}
static void spm_pinmux_setting(void)
{
clrsetbits_le32(&mtk_spm->poweron_config_set,
clrsetbits32(&mtk_spm->poweron_config_set,
(0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0));
clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
}
@@ -377,11 +377,11 @@ static void init_dram(const struct sdram_params *params, u8 freq_group,
void enable_emi_dcm(void)
{
clrbits_le32(&emi_regs->conm, 0xff << 24);
clrbits_le32(&emi_regs->conn, 0xff << 24);
clrbits32(&emi_regs->conm, 0xff << 24);
clrbits32(&emi_regs->conn, 0xff << 24);
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24);
clrbits32(&ch[chn].emi.chn_conb, 0xff << 24);
}
struct shuffle_reg_addr {
@@ -456,18 +456,18 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
value = read32(src_addr) & 0x7f;
if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
clrsetbits_le32(dst_addr, 0x7f << 0x8, value << 0x8);
clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8);
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16);
clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16);
/* DRAMC-exception-2 */
src_addr = (u8 *)&ch[chn].ao.dvfsdll;
value = (read32(src_addr) >> 1) & 0x1;
if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
clrsetbits_le32(src_addr, 0x1 << 2, value << 2);
clrsetbits32(src_addr, 0x1 << 2, value << 2);
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
clrsetbits_le32(src_addr, 0x1 << 3, value << 3);
clrsetbits32(src_addr, 0x1 << 3, value << 3);
/* PHY */
for (index = 0; index < ARRAY_SIZE(phy_regs); index++) {

32
src/soc/mediatek/mt8183/gpio.c
View File

@@ -34,15 +34,15 @@ static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
if (enable == GPIO_PULL_ENABLE) {
if (select == GPIO_PULL_DOWN)
setbits_le32(reg, 1 << (bit + 2));
setbits32(reg, 1 << (bit + 2));
else
clrbits_le32(reg, 1 << (bit + 2));
clrbits32(reg, 1 << (bit + 2));
}
if (enable == GPIO_PULL_ENABLE)
clrsetbits_le32(reg, 3 << bit, 1 << bit);
clrsetbits32(reg, 3 << bit, 1 << bit);
else
clrbits_le32(reg, 3 << bit);
clrbits32(reg, 3 << bit);
}
static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable,
@@ -53,15 +53,15 @@ static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable,
if (enable == GPIO_PULL_ENABLE) {
if (select == GPIO_PULL_DOWN)
clrbits_le32(reg + SEL_OFFSET, 1 << bit);
clrbits32(reg + SEL_OFFSET, 1 << bit);
else
setbits_le32(reg + SEL_OFFSET, 1 << bit);
setbits32(reg + SEL_OFFSET, 1 << bit);
}
if (enable == GPIO_PULL_ENABLE)
setbits_le32(reg + EN_OFFSET, 1 << bit);
setbits32(reg + EN_OFFSET, 1 << bit);
else
clrbits_le32(reg + EN_OFFSET, 1 << bit);
clrbits32(reg + EN_OFFSET, 1 << bit);
}
void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
@@ -112,23 +112,23 @@ enum {
void gpio_set_i2c_eh_rsel(void)
{
clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
clrsetbits32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) |
I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1),
I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) |
I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1));
clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
clrsetbits32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) |
I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4),
I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) |
I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4));
clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
clrsetbits32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3),
I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3));
clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
clrsetbits32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5),
I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5));
}
@@ -153,17 +153,17 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
offset = 0;
} else if (pad_select == SPI_PAD1_MASK) {
clrsetbits_le32((void *)IOCFG_RM_BASE +
clrsetbits32((void *)IOCFG_RM_BASE +
GPIO_DRV0_OFFSET, 0xf | 0xf << 20,
reg_val | reg_val << 20);
clrsetbits_le32((void *)IOCFG_RM_BASE +
clrsetbits32((void *)IOCFG_RM_BASE +
GPIO_DRV1_OFFSET, 0xf << 16,
reg_val << 16);
return;
}
break;
case 2:
clrsetbits_le32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET,
clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET,
0xf << 8 | 0xf << 12,
reg_val << 8 | reg_val << 12);
return;
@@ -181,5 +181,5 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
break;
}
clrsetbits_le32(reg, 0xf << offset, reg_val << offset);
clrsetbits32(reg, 0xf << offset, reg_val << offset);
}

4
src/soc/mediatek/mt8183/md_ctrl.c
View File

@@ -24,10 +24,10 @@
static void internal_md_power_down(void)
{
/* Gating MD clock */
setbits_le32(&mtk_topckgen->clk_mode,
setbits32(&mtk_topckgen->clk_mode,
TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M);
/* Release SRCCLKENA */
clrbits_le32(&mt8183_infracfg->infra_misc2,
clrbits32(&mt8183_infracfg->infra_misc2,
INFRA_MISC2_SRCCLKENA_RELEASE);
}

48
src/soc/mediatek/mt8183/pll.c
View File

@@ -282,7 +282,7 @@ static const struct rate rates[] = {
void pll_set_pcw_change(const struct pll *pll)
{
setbits_le32(pll->div_reg, PLL_PCW_CHG);
setbits32(pll->div_reg, PLL_PCW_CHG);
}
void mt_pll_init(void)
@@ -290,20 +290,20 @@ void mt_pll_init(void)
int i;
/* enable univpll & mainpll div */
setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
/* enable clock square1 low-pass filter */
setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
/* xPLL PWR ON */
for (i = 0; i < APMIXED_PLL_MAX; i++)
setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
setbits32(plls[i].pwr_reg, PLL_PWR_ON);
udelay(PLL_PWR_ON_DELAY);
/* xPLL ISO Disable */
for (i = 0; i < APMIXED_PLL_MAX; i++)
clrbits_le32(plls[i].pwr_reg, PLL_ISO);
clrbits32(plls[i].pwr_reg, PLL_ISO);
udelay(PLL_ISO_DELAY);
@@ -319,7 +319,7 @@ void mt_pll_init(void)
/* xPLL Frequency Enable */
for (i = 0; i < APMIXED_PLL_MAX; i++)
setbits_le32(plls[i].reg, PLL_EN);
setbits32(plls[i].reg, PLL_EN);
/* wait for PLL stable */
udelay(PLL_EN_DELAY);
@@ -327,32 +327,32 @@ void mt_pll_init(void)
/* xPLL DIV RSTB */
for (i = 0; i < APMIXED_PLL_MAX; i++) {
if (plls[i].rstb_shift != NO_RSTB_SHIFT)
setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
}
/* MCUCFG CLKMUX */
clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
MUX_SRC_ARMPLL);
clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
MUX_SRC_ARMPLL);
clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
MUX_SRC_ARMPLL);
/* enable infrasys DCM */
setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl,
setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl,
DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON);
setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl,
setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl,
DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON);
/* enable [11] for change i2c module source clock to TOPCKGEN */
setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
/*
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
@@ -361,19 +361,19 @@ void mt_pll_init(void)
mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
/* enable [14] dramc_pll104m_ck */
setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
/* enable audio clock */
setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
/* enable intbus clock */
setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
/* enable infra clock */
setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
/* enable mtkaif 26m clock */
setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
}
void mt_pll_raise_ca53_freq(u32 freq)

8
src/soc/mediatek/mt8183/spi.c
View File

@@ -127,10 +127,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
SPI_CFG1_CS_IDLE_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
SPI_CFG1_CS_IDLE_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {

14
src/soc/mediatek/mt8183/spm.c
View File

@@ -77,16 +77,16 @@ static int spm_register_init(void)
MD_DDR_EN_1_DBC_LEN |
CONN_DDR_EN_DBC_LEN);
clrsetbits_le32(&mtk_spm->spare_ack_mask,
SPARE_ACK_MASK_B_BIT1,
SPARE_ACK_MASK_B_BIT0);
clrsetbits32(&mtk_spm->spare_ack_mask,
SPARE_ACK_MASK_B_BIT1,
SPARE_ACK_MASK_B_BIT0);
write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN);
write32(&mtk_spm->spm_pc_trace_con,
SPM_PC_TRACE_OFFSET |
SPM_PC_TRACE_HW_EN_LSB);
setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB);
setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB);
return 0;
}
@@ -131,9 +131,9 @@ static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc)
write32(&mtk_spm->pcm_pwr_io_en, 0);
clrsetbits_le32(&mtk_spm->pcm_con1,
PCM_TIMER_EN_LSB,
SPM_REGWR_CFG_KEY);
clrsetbits32(&mtk_spm->pcm_con1,
PCM_TIMER_EN_LSB,
SPM_REGWR_CFG_KEY);
write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
PCM_SW_RESET_LSB);

2
src/soc/mediatek/mt8183/sspm.c
View File

@@ -16,7 +16,7 @@
#include <arch/barrier.h>
#include <cbfs.h>
#include <console/console.h>
#include <arch/mmio.h>
#include <device/mmio.h>
#include <soc/sspm.h>
#include <string.h>