sravan/system76-coreboot
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Change all clrsetbits_leXX() to clrsetbitsXX()

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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Julius Werner
2019-12-02 22:03:27 -08:00
committed by Patrick Georgi
parent 1c37157218
commit 55009af42c
108 changed files with 2022 additions and 2025 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/mediatek/common/ddp.c
View File

@@ -31,7 +31,7 @@ void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
void rdma_start(void)
{
setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN);
}
void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
@@ -39,8 +39,8 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
u32 threshold;
u32 reg;
clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width);
clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height);
clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width);
clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height);
/*
* Enable FIFO underflow since DSI and DPI can't be blocked. Set the
@@ -78,5 +78,5 @@ void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height)
write32(&ovl0->rdma[0].ctrl, BIT(0));
write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
setbits_le32(&ovl0->src_con, BIT(0));
setbits32(&ovl0->src_con, BIT(0));
}

8
src/soc/mediatek/common/dsi.c
View File

@@ -120,12 +120,12 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing)
static void mtk_dsi_clk_hs_mode_enable(void)
{
setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
setbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
}
static void mtk_dsi_clk_hs_mode_disable(void)
{
clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
clrbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN);
}
static void mtk_dsi_set_mode(u32 mode_flags)
@@ -394,8 +394,8 @@ static void mtk_dsi_send_init_commands(const u8 *buf)
static void mtk_dsi_reset_dphy(void)
{
setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
}
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,

3
src/soc/mediatek/common/gpio.c
View File

@@ -63,8 +63,7 @@ void gpio_set_mode(gpio_t gpio, int mode)
pos_bit_calc_for_mode(gpio, &pos, &bit);
clrsetbits_le32(&mtk_gpio->mode[pos].val,
mask << bit, mode << bit);
clrsetbits32(&mtk_gpio->mode[pos].val, mask << bit, mode << bit);
}
int gpio_get(gpio_t gpio)

12
src/soc/mediatek/common/mtcmos.c
View File

@@ -46,17 +46,17 @@ static void mtcmos_power_on(const struct power_domain_data *pd)
write32(&mtk_spm->poweron_config_set,
(SPM_PROJECT_CODE << 16) | (1U << 0));
setbits_le32(pd->pwr_con, PWR_ON);
setbits_le32(pd->pwr_con, PWR_ON_2ND);
setbits32(pd->pwr_con, PWR_ON);
setbits32(pd->pwr_con, PWR_ON_2ND);
while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
!(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
continue;
clrbits_le32(pd->pwr_con, PWR_CLK_DIS);
clrbits_le32(pd->pwr_con, PWR_ISO);
setbits_le32(pd->pwr_con, PWR_RST_B);
clrbits_le32(pd->pwr_con, pd->sram_pdn_mask);
clrbits32(pd->pwr_con, PWR_CLK_DIS);
clrbits32(pd->pwr_con, PWR_ISO);
setbits32(pd->pwr_con, PWR_RST_B);
clrbits32(pd->pwr_con, pd->sram_pdn_mask);
while (read32(pd->pwr_con) & pd->sram_ack_mask)
continue;

36
src/soc/mediatek/common/spi.c
View File

@@ -50,8 +50,8 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave)
static void spi_sw_reset(struct mtk_spi_regs *regs)
{
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
clrbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
}
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
@@ -77,17 +77,17 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly);
clrsetbits_le32(&regs->spi_cmd_reg,
(SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN |
SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN |
SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN |
SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN),
(SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN |
SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN));
clrsetbits32(&regs->spi_cmd_reg,
(SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN |
SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN |
SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN |
SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN),
(SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN |
SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN));
mtk_spi_set_gpio_pinmux(bus, pad_select);
clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK,
clrsetbits32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK,
pad_select);
gpio_output(slave->cs_gpio, 1);
@@ -110,7 +110,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave);
struct mtk_spi_regs *regs = mtk_slave->regs;
setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT);
setbits32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT);
mtk_slave->state = MTK_SPI_IDLE;
gpio_output(mtk_slave->cs_gpio, 0);
@@ -135,10 +135,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
else
size = MIN(*bytes_in, *bytes_out);
clrsetbits_le32(&regs->spi_cfg1_reg,
SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK,
((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
(0 << SPI_CFG1_PACKET_LOOP_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg,
SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK,
((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
(0 << SPI_CFG1_PACKET_LOOP_SHIFT));
if (*bytes_out) {
const uint8_t *outb = (const uint8_t *)out;
@@ -166,10 +166,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
}
if (mtk_slave->state == MTK_SPI_IDLE) {
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN);
mtk_slave->state = MTK_SPI_PAUSE_IDLE;
} else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) {
setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN);
setbits32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN);
}
stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US);
@@ -246,7 +246,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave);
struct mtk_spi_regs *regs = mtk_slave->regs;
clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN);
clrbits32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN);
spi_sw_reset(regs);
mtk_slave->state = MTK_SPI_IDLE;

4
src/soc/mediatek/common/timer.c
View File

@@ -48,8 +48,8 @@ void init_timer(void)
timer_prepare();
/* Disable timer and clear the counter */
clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN);
setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN);
setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR);
/* Set clock source to system clock and set clock divider to 1 */
write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1);

46
src/soc/mediatek/common/usb.c
View File

@@ -32,53 +32,53 @@ static void phy_index_power_on(int index)
if (!index) {
/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
setbits32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON);
/* Disable power domain ISO */
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN);
}
/* Switch system IP to USB mode */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN);
clrbits32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN);
if (!index)
clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
clrbits32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK);
/* Disable force settings */
clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM |
P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN);
/* Improve Rx sensitivity */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
clrsetbits32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
setbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN);
clrsetbits_le32(&phy->u3phya_da.reg0,
clrsetbits32(&phy->u3phya_da.reg0,
P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
clrsetbits_le32(&phy->u3phya.phya_reg9,
clrsetbits32(&phy->u3phya.phya_reg9,
P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
if (!index)
clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
clrbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN);
clrsetbits_le32(&phy->u3phya.phya_reg6,
clrsetbits32(&phy->u3phya.phya_reg6,
P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
clrsetbits32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc));
clrsetbits_le32(&phy->u3phyd.phyd_cdr1,
clrsetbits32(&phy->u3phyd.phyd_cdr1,
P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3));
clrsetbits_le32(&phy->u2phy.u2phydtm1,
clrsetbits32(&phy->u2phy.u2phydtm1,
P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
/* Set USB 2.0 slew rate value */
clrsetbits_le32(&phy->u2phy.usbphyacr5,
clrsetbits32(&phy->u2phy.usbphyacr5,
PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
/* Set USB 2.0 disconnect threshold */
clrsetbits_le32(&phy->u2phy.usbphyacr6,
clrsetbits32(&phy->u2phy.usbphyacr6,
PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
}
@@ -128,18 +128,18 @@ static int u3phy_ports_enable(void)
u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num);
/* Power on host ip */
clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
clrbits32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN);
/* Power on and enable all u3 ports */
for (i = 0; i < u3_port_num; i++) {
clrsetbits_le32(&ippc_regs->u3_ctrl_p[i],
clrsetbits32(&ippc_regs->u3_ctrl_p[i],
CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
CTRL_U3_PORT_HOST_SEL);
}
/* Power on and enable all u2 ports */
for (i = 0; i < u2_port_num; i++) {
clrsetbits_le32(&ippc_regs->u2_ctrl_p[i],
clrsetbits32(&ippc_regs->u2_ctrl_p[i],
CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
CTRL_U2_PORT_HOST_SEL);
}
@@ -149,8 +149,8 @@ static int u3phy_ports_enable(void)
static inline void ssusb_soft_reset(void)
{
/* Reset whole ip */
setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
setbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST);
}
__weak void mtk_usb_prepare(void) { /* do nothing */ }

8
src/soc/mediatek/common/wdt.c
View File

@@ -45,10 +45,10 @@ int mtk_wdt_init(void)
* ENABLE: disable watchdog on initialization.
* Setting bit EXTEN to enable watchdog output.
*/
clrsetbits_le32(&mtk_wdt->wdt_mode,
MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
clrsetbits32(&mtk_wdt->wdt_mode,
MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
return wdt_sta;
}