soc/intel/common: prepare for lpss clock split

Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.

BUG=b:75306520

Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/Kconfig

@@ -30,13 +30,6 @@ config ACPI_CONSOLE
 	help
 	  Provide a mechanism for serial console based ACPI debug.
 
-config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
-	int
-	help
-	  The clock speed that the controllers in LPSS(GSPI, I2C) are running
-	  at, in MHz. No default is set here as this is an SOC-specific value
-	  and must be provided by the SOC.
-
 config MMA
 	bool "Enable MMA (Memory Margin Analysis) support for Intel Core"
 	default n