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google/fizz: Disable unused i2c lines

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As cr50 has now switched to using SPI, no need to enable the i2c1
anymore.  Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.

BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron.  Make sure /dev/tpm0 created on (many)
     reboots.  cat /proc/interrupts.  Make sure # interrupts for 16
     after booting is reasonable (not > 10k)  and idma64.0,
     i2c_designware.0 are not listed with that interrupt line anymore.
     Should look something like this:

     16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP

Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen
2017-11-22 16:55:27 -08:00
committed by Shelley Chen
parent 6fd5a79d47
commit 5537f02bd5
1 changed files with 7 additions and 21 deletions
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28
src/mainboard/google/fizz/devicetree.cb
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@@ -233,17 +233,11 @@ chip soc/intel/skylake
.early_init = 1, .early_init = 1,
}" }"
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
.early_init = 1,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
@@ -273,18 +267,10 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem device pci 14.2 on end # Thermal Subsystem
device pci 15.0 on device pci 15.0 off end # I2C #0
end # I2C #0 device pci 15.1 off end # I2C #1
device pci 15.1 on device pci 15.2 off end # I2C #2
chip drivers/i2c/tpm device pci 15.3 off end # I2C #3
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device i2c 50 on end
end
end # I2C #1
device pci 15.2 on end # I2C #2
device pci 15.3 off
end # I2C #3
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R