soc/intel/tigerlake: Remove Jasper Lake SoC references

This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.

BUG=b:150217037
TEST=build tglrvp and volteer

Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/intel/tglrvp/romstage_fsp_params.c

@@ -17,7 +17,7 @@
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <string.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <baseboard/variants.h>
 #include <cbfs.h>
 #include "board_id.h"

src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h

@@ -16,7 +16,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>