soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aamir Bohra
committed by
Furquan Shaikh
Furquan Shaikh
parent
a23e0c9d74
commit
555c9b6268
213
src/soc/intel/tigerlake/fsp_params.c
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213
src/soc/intel/tigerlake/fsp_params.c
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/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/xdci.h>
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#include <soc/gpio_soc_defs.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include <string.h>
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/*
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* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
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* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
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* In order to ensure that mainboard setting does not disable L1 substates
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* incorrectly, chip config parameter values are offset by 1 with 0 meaning
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* use FSP UPD default. get_l1_substate_control() ensures that the right UPD
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* value is set in fsp_params.
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* 0: Use FSP UPD default
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* 1: Disable L1 substates
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* 2: Use L1.1
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* 3: Use L1.2 (FSP UPD default)
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*/
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static int get_l1_substate_control(enum L1_substates_control ctl)
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{
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if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
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ctl = L1_SS_L1_2;
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return ctl - 1;
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}
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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const struct soc_intel_tigerlake_config *config;
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config = config_of_soc();
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for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
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params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
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for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
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params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
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params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
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params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
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}
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for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
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params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
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}
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_GSPI3,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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int i;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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struct device *dev;
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struct soc_intel_tigerlake_config *config;
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config = config_of_soc();
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/* Parse device tree and enable/disable Serial I/O devices */
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parse_devicetree(params);
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/* Load VBT before devicetree-specific config. */
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params->GraphicsConfigPtr = (uintptr_t)vbt_get();
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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params->TcssAuxOri = config->TcssAuxOri;
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for (i = 0; i < 8; i++)
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params->IomTypeCPortPadCfg[i] = 0x09000000;
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/* USB */
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
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params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
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params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
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params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
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params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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/* RP Configs */
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for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
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params->PcieRpL1Substates[i] =
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get_l1_substate_control(config->PcieRpL1Substates[i]);
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
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if (dev) {
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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} else {
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params->XdciEnable = 0;
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}
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/* PCH UART selection for FSP Debug */
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params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
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params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
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/* SATA */
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dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
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if (!dev)
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params->SataEnable = 0;
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else {
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params->SataEnable = dev->enabled;
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params->SataMode = config->SataMode;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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}
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/* LAN */
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dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
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if (!dev)
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params->PchLanEnable = 0;
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else
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params->PchLanEnable = dev->enabled;
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/* CNVi */
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dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
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if (dev)
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params->CnviMode = dev->enabled;
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else
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params->CnviMode = 0;
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
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params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
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/* Enable Hybrid storage auto detection */
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params->HybridStorageMode = config->HybridStorageMode;
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/* USB4/TBT */
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for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
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dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
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if (dev)
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params->ITbtPcieRootPortEn[i] = dev->enabled;
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else
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params->ITbtPcieRootPortEn[i] = 0;
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}
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mainboard_silicon_init_params(params);
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}
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/* Mainboard GPIO Configuration */
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__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Return list of SOC LPSS controllers */
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const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
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{
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*size = ARRAY_SIZE(serial_io_dev);
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return serial_io_dev;
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}
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