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i945: consolidate sb & nb early inits

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Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7062
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Vladimir Serbinenko
2014-10-15 20:17:51 +02:00
parent 385743acbc
commit 5560188849
12 changed files with 112 additions and 383 deletions
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26
src/southbridge/intel/i82801gx/early_lpc.c
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@ -20,6 +20,9 @@
#include <arch/io.h>
#include <timestamp.h>
#include <console/console.h>
#include <arch/acpi.h>
#include "i82801gx.h"
#if CONFIG_COLLECT_TIMESTAMPS
tsc_t get_initial_timestamp(void)
@ -31,3 +34,26 @@ tsc_t get_initial_timestamp(void)
return base_time;
}
#endif
int southbridge_detect_s3_resume(void)
{
u32 reg32;
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
return 1;
} else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
}
}
return 0;
}