soc/amd/*/i2c: factor out common I2C pad configuration

The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO  for future improvements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/picasso/Kconfig

@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_HDA
 	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX